On 6/4/23 03:28, Nicholas Piggin wrote:
Rework store conditional to avoid a branch in the success case.
Change some of the variable names and layout while here so
gen_conditional_store more closely matches gen_stqcx_.
Signed-off-by: Nicholas Piggin <npig...@gmail.com>
---
target/ppc/translate.c | 65 ++++++++++++++++++++----------------------
1 file changed, 31 insertions(+), 34 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 77e1c5abb6..cf99e961f7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3812,31 +3812,32 @@ static void gen_stdat(DisasContext *ctx)
static void gen_conditional_store(DisasContext *ctx, MemOp memop)
{
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGv t0 = tcg_temp_new();
- int reg = rS(ctx->opcode);
+ TCGLabel *lfail;
+ TCGv EA;
+ TCGv cr0;
+ TCGv t0;
+ int rs = rS(ctx->opcode);
+ lfail = gen_new_label();
+ EA = tcg_temp_new();
+ cr0 = tcg_temp_new();
+ t0 = tcg_temp_new();
+
+ tcg_gen_mov_tl(cr0, cpu_so);
gen_set_access_type(ctx, ACCESS_RES);
- gen_addr_reg_index(ctx, t0);
- tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
- tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_size, memop_size(memop), l1);
+ gen_addr_reg_index(ctx, EA);
+ tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail);
+ tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_size, memop_size(memop),
lfail);
- t0 = tcg_temp_new();
tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
- cpu_gpr[reg], ctx->mem_idx,
- DEF_MEMOP(memop) | MO_ALIGN);
+ cpu_gpr[rs], ctx->mem_idx,
+ memop | MO_ALIGN);
Lost DEF_MEMOP here. Otherwise,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
