On Wed, Jun 21, 2023 at 1:25 AM Daniel Henrique Barboza <dbarb...@ventanamicro.com> wrote: > > Commit 7f0bdfb5bfc2 ("target/riscv/cpu.c: remove cfg setup from > riscv_cpu_init()") removed code that was enabling mmu, pmp, ext_ifencei > and ext_icsr from riscv_cpu_init(), the init() function of > TYPE_RISCV_CPU, parent type of all RISC-V CPUss. This was done to force > CPUs to explictly enable all extensions and features it requires, > without any 'magic values' that were inherited by the parent type. > > This commit failed to make appropriate changes in the 'veyron-v1' CPU, > added earlier by commit e1d084a8524a. The result is that the veyron-v1 > CPU has ext_ifencei, ext_icsr and pmp set to 'false', which is not the > case. > > The reason why it took this long to notice (thanks LIU Zhiwei for > reporting it) is because Linux doesn't mind 'ifencei' and 'icsr' being > absent in the 'riscv,isa' DT, implying that they're both present if the > 'i' extension is enabled. OpenSBI also doesn't error out or warns about > the lack of 'pmp', it'll just not protect memory pages. > > Fix it by setting them to 'true' in rv64_veyron_v1_cpu_init() like > 7f0bdfb5bfc2 already did with other CPUs. > > Reported-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com> > Fixes: 7f0bdfb5bfc2 ("target/riscv/cpu.c: remove cfg setup from > riscv_cpu_init()") > Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/cpu.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 881bddf393..707f62b592 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -444,6 +444,9 @@ static void rv64_veyron_v1_cpu_init(Object *obj) > > /* Enable ISA extensions */ > cpu->cfg.mmu = true; > + cpu->cfg.ext_ifencei = true; > + cpu->cfg.ext_icsr = true; > + cpu->cfg.pmp = true; > cpu->cfg.ext_icbom = true; > cpu->cfg.cbom_blocksize = 64; > cpu->cfg.cboz_blocksize = 64; > -- > 2.41.0 > >