On Tue, 27 Jun 2023 14:10:17 +0800
Xiaoyao Li <xiaoyao...@intel.com> wrote:
> On 6/26/2023 9:15 PM, Igor Mammedov wrote:
> > On Fri, 16 Jun 2023 11:23:09 +0800
> > Tao Su <tao1...@linux.intel.com> wrote:
> >
> >> From: Lei Wang <lei4.w...@intel.com>
> >>
> >> Latest stepping (8) of SapphireRapids has bit 13, 14 and 15 of
> >> MSR_IA32_ARCH_CAPABILITIES enabled, which are related to some security
> >> fixes.
> >>
> >> Add version 2 of SapphireRapids CPU model with those bits enabled also.
> >
> > don't we need to update stepping value to 8 as well?
>
> No need.
>
> The commit message is misleading. There 3 bits and some other bits in
> MSR_IA32_ARCH_CAPABILITIES are not tied to CPU stepping. Instead, they
> are enumerated with newer microcode.
It that case fix commit message please.
>
> >>
> >> Signed-off-by: Lei Wang <lei4.w...@intel.com>
> >> Signed-off-by: Tao Su <tao1...@linux.intel.com>
> >> ---
> >> target/i386/cpu.c | 13 +++++++++++--
> >> 1 file changed, 11 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> >> index b5321240c6..f84fd20bb1 100644
> >> --- a/target/i386/cpu.c
> >> +++ b/target/i386/cpu.c
> >> @@ -3854,8 +3854,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> >> .model_id = "Intel Xeon Processor (SapphireRapids)",
> >> .versions = (X86CPUVersionDefinition[]) {
> >> { .version = 1 },
> >> - { /* end of list */ },
> >> - },
> >> + {
> >> + .version = 2,
> >> + .props = (PropValue[]) {
> >> + { "sbdr-ssdp-no", "on" },
> >> + { "fbsdp-no", "on" },
> >> + { "psdp-no", "on" },
> >> + { /* end of list */ }
> >> + }
> >> + },
> >> + { /* end of list */ }
> >> + }
> >> },
> >> {
> >> .name = "Denverton",
> >
>
