On Wed, 5 Jul 2023 at 15:09, Richard Henderson <richard.hender...@linaro.org> wrote: > > On 7/4/23 15:06, Peter Maydell wrote: > > If you're checking the values against the TRM, note that the > > summary tables differ from the register description in the TRM > > for ID_AA64DFR0_EL1, ID_AA64ZFR0_EL1 and ID_PFR0_EL1: we > > trust the versions in the register descriptions. Also the > > MIDR value in the r1p2 TRM isn't updated from r1p1. > > The CCSIDR_EL1 values in the TRM unfortunately seem to be wrong: > > the comment in the patch describes how I've calculated the > > values used here. > ... > > + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; > > I see 0x0220011102101011, not in your list of exceptions above.
Good catch -- I must have cut-and-pasted the neoverse-n1 code and then forgotten to update that value in it. -- PMM
