Signed-off-by: Michael Tokarev <m...@tls.msk.ru>
---
tcg/aarch64/tcg-target.c.inc | 2 +-
tcg/arm/tcg-target.c.inc | 4 ++--
tcg/riscv/tcg-target.c.inc | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 35ca80cd56..5471523f4c 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -3088,3 +3088,3 @@ static void tcg_target_qemu_prologue(TCGContext *s)
* Note that XZR cannot be encoded in the address base register slot,
- * as that actaully encodes SP. Depending on the guest, we may need
+ * as that actually encodes SP. Depending on the guest, we may need
* to zero-extend the guest address via the address index register slot,
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 83e286088f..3a14f52c51 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1218,3 +1218,3 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg
*args,
case TCG_COND_GEU:
- /* We perform a conditional comparision. If the high half is
+ /* We perform a conditional comparison. If the high half is
equal, then overwrite the flags with the comparison of the
@@ -1252,3 +1252,3 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg
*args,
* Note that TCGReg references Q-registers.
- * Q-regno = 2 * D-regno, so shift left by 1 whlie inserting.
+ * Q-regno = 2 * D-regno, so shift left by 1 while inserting.
*/
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index eeaeb6b6e3..e9e5968823 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -71,3 +71,3 @@ static const int tcg_target_reg_alloc_order[] = {
/* Call saved registers */
- /* TCG_REG_S0 reservered for TCG_AREG0 */
+ /* TCG_REG_S0 reserved for TCG_AREG0 */
TCG_REG_S1,
@@ -262,3 +262,3 @@ typedef enum {
- /* Zbb: Bit manipulation extension, basic bit manipulaton */
+ /* Zbb: Bit manipulation extension, basic bit manipulation */
OPC_ANDN = 0x40007033,
--
2.39.2
