The RISC-V IOMMU specification is now ratified as-per the RISC-V international process [1]. The latest frozen specifcation can be found at: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
This series introduces a RISC-V IOMMU device emulation implementation with two stage address translation logic, device and process translation context mapping and queue interfaces, along with riscv/virt machine bindings (patch 5) and memory attributes extensions for PASID support (patch 3,4). This series is based on incremental patches created during RISC-V International IOMMU Task Group discussions and specification development process, with original series available in the the maintainer's repository branch [2]. These patches can also be found in the riscv_iommu_v1 branch at: https://github.com/tjeznach/qemu/tree/riscv_iommu_v1 To test this series, use Linux v6.5-rc2 with RISC-V IOMMU implementation available in the riscv_iommu_v1 branch at: https://github.com/tjeznach/linux/tree/riscv_iommu_v1 References: [1] - https://wiki.riscv.org/display/HOME/Specification+Status [2] - https://github.com/tjeznach/qemu/tree/tjeznach/riscv-iommu-20230719 Tomasz Jeznach (5): hw/riscv: Introduction of RISC-V IOMMU device MAINTAINERS: Add RISC-V IOMMU maintainers exec/memtxattr: add process identifier to the transaction attributes hw/riscv: IOMMU: use process identifier from transaction attributes. hw/riscv: virt: support for RISC-V IOMMU platform device. MAINTAINERS | 6 + hw/riscv/Kconfig | 4 + hw/riscv/meson.build | 1 + hw/riscv/riscv-iommu-bits.h | 749 +++++++++++ hw/riscv/riscv-iommu-pci.c | 181 +++ hw/riscv/riscv-iommu-sys.c | 123 ++ hw/riscv/riscv-iommu.c | 2546 +++++++++++++++++++++++++++++++++++ hw/riscv/riscv-iommu.h | 152 +++ hw/riscv/trace-events | 14 + hw/riscv/trace.h | 2 + hw/riscv/virt.c | 100 +- include/exec/memattrs.h | 6 + include/hw/riscv/iommu.h | 40 + include/hw/riscv/virt.h | 3 + meson.build | 1 + 15 files changed, 3927 insertions(+), 1 deletion(-) create mode 100644 hw/riscv/riscv-iommu-bits.h create mode 100644 hw/riscv/riscv-iommu-pci.c create mode 100644 hw/riscv/riscv-iommu-sys.c create mode 100644 hw/riscv/riscv-iommu.c create mode 100644 hw/riscv/riscv-iommu.h create mode 100644 hw/riscv/trace-events create mode 100644 hw/riscv/trace.h create mode 100644 include/hw/riscv/iommu.h -- 2.34.1