On 7/26/23 08:01, Richard Henderson wrote:
On 7/26/23 01:17, Ard Biesheuvel wrote:
Hints welcome on where the architectural behavior is specified, and in
particular,
whether or not other 64-bit GPRs can be relied upon to preserve their full
64-bit
length values.
No idea about chapter and verse, but it has the feel of being part and parcel
with the
truncation of eip. While esp is always special, I suspect that none of the GPRs can be
relied on carrying all bits.
Coincidentally, I was having a gander at the newly announced APX extension [1],
and happened across
3.1.4.1.2 Extended GPR Access (Direct and Indirect)
... Entering/leaving 64-bit mode via traditional (explicit)
control flow does not directly alter the content of the EGPRs
(EGPRs behave similar to R8-R15 in this regard).
which suggests to me that the 8 low registers are squashed to 32-bit
on transition to 32-bit IA-32e mode.
I still have not found similar language in the main architecture manual.
r~
[1]
https://www.intel.com/content/www/us/en/content-details/784266/intel-advanced-performance-extensions-intel-apx-architecture-specification.html
