Hi Zhao,
On 8/4/23 04:56, Zhao Liu wrote:
> Hi Babu,
>
> On Thu, Aug 03, 2023 at 03:44:13PM -0500, Moger, Babu wrote:
>> Date: Thu, 3 Aug 2023 15:44:13 -0500
>> From: "Moger, Babu" <babu.mo...@amd.com>
>> Subject: Re: [PATCH v3 16/17] i386: Use CPUCacheInfo.share_level to encode
>> CPUID[0x8000001D].EAX[bits 25:14]
>>
>> Hi Zhao,
>> Please copy the thread to k...@vger.kernel.org also. It makes it easier
>> to browse.
>>
>
> OK. I'm not sure how to cc, should I forward all mail to KVM for the
> current version (v3), or should I cc the kvm mail list for the next
> version (v4)?
Yes. From v4.
Thanks
Babu
>
>>
>> On 8/1/23 05:35, Zhao Liu wrote:
>>> From: Zhao Liu <zhao1....@intel.com>
>>>
>>> CPUID[0x8000001D].EAX[bits 25:14] is used to represent the cache
>>> topology for amd CPUs.
>> Please change this to.
>>
>>
>> CPUID[0x8000001D].EAX[bits 25:14] NumSharingCache: number of logical
>> processors sharing cache. The number of
>> logical processors sharing this cache is NumSharingCache + 1.
>
> OK.
>
> Thanks,
> Zhao
>
>>
>>>
>>> After cache models have topology information, we can use
>>> CPUCacheInfo.share_level to decide which topology level to be encoded
>>> into CPUID[0x8000001D].EAX[bits 25:14].
>>>
>>> Signed-off-by: Zhao Liu <zhao1....@intel.com>
>>> ---
>>> Changes since v1:
>>> * Use cache->share_level as the parameter in
>>> max_processor_ids_for_cache().
>>> ---
>>> target/i386/cpu.c | 10 +---------
>>> 1 file changed, 1 insertion(+), 9 deletions(-)
>>>
>>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>>> index f67b6be10b8d..6eee0274ade4 100644
>>> --- a/target/i386/cpu.c
>>> +++ b/target/i386/cpu.c
>>> @@ -361,20 +361,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo
>>> *cache,
>>> uint32_t *eax, uint32_t *ebx,
>>> uint32_t *ecx, uint32_t *edx)
>>> {
>>> - uint32_t num_apic_ids;
>>> assert(cache->size == cache->line_size * cache->associativity *
>>> cache->partitions * cache->sets);
>>>
>>> *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
>>> (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
>>> -
>>> - /* L3 is shared among multiple cores */
>>> - if (cache->level == 3) {
>>> - num_apic_ids = 1 << apicid_die_offset(topo_info);
>>> - } else {
>>> - num_apic_ids = 1 << apicid_core_offset(topo_info);
>>> - }
>>> - *eax |= (num_apic_ids - 1) << 14;
>>> + *eax |= max_processor_ids_for_cache(topo_info, cache->share_level) <<
>>> 14;
>>>
>>> assert(cache->line_size > 0);
>>> assert(cache->partitions > 0);
>>
>> --
>> Thanks
>> Babu Moger
--
Thanks
Babu Moger
