Re: [PATCH] linux-user/elfload: Set V in ELF_HWCAP for RISC-V

[Michael Tokarev]

03.08.2023 16:14, Nathan Egge wrote:

From: "Nathan Egge" <ne...@xiph.org>

Set V bit for hwcap if misa is set.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793
Signed-off-by: Nathan Egge <ne...@xiph.org>
---
  linux-user/elfload.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 861ec07abc..a299ba7300 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1710,7 +1710,8 @@ static uint32_t get_elf_hwcap(void)
  #define MISA_BIT(EXT) (1 << (EXT - 'A'))
      RISCVCPU *cpu = RISCV_CPU(thread_cpu);
      uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
-                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
+                    | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C')
+                    | MISA_BIT('V');

Is smells like a -stable material (incl. 7.2), is it not?

Thanks,

/mjt