On Tue, Aug 8, 2023 at 5:16 PM Palmer Dabbelt <pal...@rivosinc.com> wrote: > > On Tue, 08 Aug 2023 14:10:54 PDT (-0700), dbarb...@ventanamicro.com wrote: > > > > > > On 8/8/23 17:52, Palmer Dabbelt wrote: > >> On Tue, 08 Aug 2023 11:45:49 PDT (-0700), Vineet Gupta wrote: > >>> > >>> > >>> On 8/8/23 11:29, Richard Henderson wrote: > >>>> On 8/8/23 11:17, Vineet Gupta wrote: > >>>>> zicond is now codegen supported in both llvm and gcc. > >>>> > >>>> It is still not in > >>>> > >>>> https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions > >>> > >>> Right, its been frozen since April though and with support trickling in > >>> rest of tooling it becomes harder to test. > >>> I don't know what exactly QEMU's policy is on this ? > >> > >> IIUC we'd historically marked stuff as non-experimental when it's frozen, > >> largely because ratification is such a nebulous process. There's obviously > >> risk there, but there's risk to anything. Last I can find is 260b594d8a > >> ("RISC-V: Add Zawrs ISA extension support"), which specifically calls out > >> Zawrs as frozen and IIUC adds support without the "x-" prefix. > > > > If that's the case then I think it's sensible to remove the 'experimental' > > status > > of zicond as well. > > > >> > >> I can't find anything written down about it, though... > > > > As soon as we agree on an official policy I'll do a doc update. Thanks, > > Thanks. We should probably give Alistair some time to chime in, it's > still pretty early there.
Frozen should be enough to remove the `x-`. We do have it written down at: https://wiki.qemu.org/Documentation/Platforms/RISCV#RISC-V_Foundation_Extensions Alistair > > > > > > > Daniel > > > >> >
