On Thu, 10 Aug 2023 at 20:16, Francisco Iglesias <francisco.igles...@amd.com> wrote: > > Introduce a model of Xilinx Versal's Configuration Frame Unit's data out > port (CFU_FDRO). > > Signed-off-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
