On 02/23/2012 02:49 AM, Zhang, Yang Z wrote: >> > 6) Setting the clock after 500 ms happens not on every set, but only when >> > moving >> > out of divider reset (register A bits 5-7 moving from 110 or 111 to 010). >> > As far as >> > I can read, SET prevents the registers from changing value, but keeps the >> > internal >> > sub-second counters running. > Do we really need this logic? It sounds like senseless.
It doesn't seem hard to do, see my branch. Paolo
