On Tue, 5 Sep 2023 18:45:02 +0800 Yuquan Wang <wangyuquan1...@phytium.com.cn> wrote:
> Hi, Jonathan > On 2023-09-04 20:43, jonathan.cameron wrote: > > > > At the system design level, MMIO space of Root complex register space via > > RCRB > > does not map in a similar fashion to PCIE MMIO space (which is handled via > > address decoding in the PCIE fabric). It is much more similar to MMIO for > > platform > > devices - as such the implementation handles in like a platform device > > (well 16 of > > them which seemed enough for any sane usecase). > > > > > > Oh,thanks! According to above, therefore, the core factor is the > implementation of RCRB. > > > > > So in theory we could make some space for the CXL root bridge RCRB registers > > but it would make various generic paths more complex. In a real system > > those registers are likely to be far from the PCI MMIO space anyway so the > > way it's modeled is probably more realistic than pushing the RCRB into the > > existing allocation. > > > > Here implies that all CXL root bridge will use RCRB registers. > > From Table 8-17 and Figure 9-14 in CXL3.0 specification, I understood that > only RCH DP & > RCD UP will use RCRBs, and CXL host bridges VH mode will use other way to > realize > the CHBCR. I had tried to find more explanation in CXL spec, but I haven't > found. Hence > this is why I am confused. Ah. That distinction is a bit messy. Both an RCRB and CHBCR (CXL Host Bridge Component Registers) are similar in the sense that they are mapped in host memory space. As I understand it the distinction is more about the format / contents of that memory than how you access them. As an aside, they are described by a static ACPI table, so they can't be in the MMIO space used for BARs etc. Jonathan > > Many thanks > Yuquan
