From: Richard Henderson <richard.hender...@linaro.org>
Typo applied byte-wise shift instead of double-word shift.
Cc: qemu-sta...@nongnu.org
Fixes: 631e565450c ("target/arm: Create gen_gvec_[us]sra")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1737
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20230821022025.397682-1-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
(cherry picked from commit cd1e4db73646006039f25879af3bff55b2295ff3)
Signed-off-by: Michael Tokarev <m...@tls.msk.ru>
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 9cf4a6819e..10dfa11a2b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3138,7 +3138,7 @@ void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs,
uint32_t rm_ofs,
.vece = MO_32 },
{ .fni8 = gen_ssra64_i64,
.fniv = gen_ssra_vec,
- .fno = gen_helper_gvec_ssra_b,
+ .fno = gen_helper_gvec_ssra_d,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.opt_opc = vecop_list,
.load_dest = true,
--
2.39.2
