Hey Daniel, Sorry I was on holiday. There is no new work on this AFAIK. I will rebase and send a new version for this shortly.
Thanks Rajnesh On Wed, Sep 6, 2023 at 3:38 PM Daniel Henrique Barboza <dbarb...@ventanamicro.com> wrote: > > Hey, > > > What's the latest on this work? It seems that all patches are acked: > > https://lore.kernel.org/qemu-riscv/20230526162308.22892-1-rkan...@rivosinc.com/ > > > It'll probably conflict with current Alistair's riscv-to-apply.next though, so > perhaps Rajnesh could gather the acks and send a rebased version. > > > Thanks, > > Daniel > > > On 5/26/23 13:23, Rajnesh Kanwal wrote: > > This series adds M and HS-mode virtual interrupt and IRQ filtering support. > > This allows inserting virtual interrupts from M/HS-mode into S/VS-mode > > using mvien/hvien and mvip/hvip csrs. IRQ filtering is a use case of > > this change, i-e M-mode can stop delegating an interrupt to S-mode and > > instead enable it in MIE and receive those interrupts in M-mode and then > > selectively inject the interrupt using mvien and mvip. > > > > Also, the spec doesn't mandate the interrupt to be actually supported > > in hardware. Which allows M/HS-mode to assert virtual interrupts to > > S/VS-mode that have no connection to any real interrupt events. > > > > This is defined as part of the AIA specification [0], "5.3 Interrupt > > filtering and virtual interrupts for supervisor level" and "6.3.2 Virtual > > interrupts for VS level". > > > > Most of the testing is done by hacking around OpenSBI and linux host. > > The changes for those can be found at [1] and [2]. > > > > It's my first touch on RISC-V qemu IRQ subsystem. Any feedback would > > be much appreciated. > > > > The change can also be found on github [3]. > > > > TODO: This change doesn't support delegating virtual interrupts injected > > by M-mode to VS-mode by the Hypervisor. This is true for bits 13:63 only. > > > > Thanks > > Rajnesh > > > > [0]: > > https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-interrupts-1.0-RC4.pdf > > [1]: https://github.com/rajnesh-kanwal/opensbi/tree/dev/rkanwal/irq_filter > > [2]: > > https://github.com/rajnesh-kanwal/linux/commits/dev/rkanwal/aia_irq_filter > > [3]: > > https://github.com/rajnesh-kanwal/qemu/tree/dev/rkanwal/riscv_irq_filter > > > > v2: > > * Move RISCV_EXCP_SEMIHOST to switch case and remove special handling. > > * Fix linux-user build. > > > > Rajnesh Kanwal (6): > > target/riscv: Without H-mode mask all HS mode inturrupts in mie. > > target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. > > target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled > > target/riscv: Split interrupt logic from riscv_cpu_update_mip. > > target/riscv: Add M-mode virtual interrupt and IRQ filtering support. > > target/riscv: Add HS-mode virtual interrupt and IRQ filtering support. > > > > target/riscv/cpu.c | 9 +- > > target/riscv/cpu.h | 23 ++ > > target/riscv/cpu_bits.h | 6 + > > target/riscv/cpu_helper.c | 99 +++++--- > > target/riscv/csr.c | 477 ++++++++++++++++++++++++++++++++++---- > > target/riscv/machine.c | 6 + > > 6 files changed, 546 insertions(+), 74 deletions(-) > >