Public bug reported: qemu version 0.15.1 but the same code is in qemu 1.0
"CPSID I" does not disable interrupts for CORTEX M3 if (interrupt_request & CPU_INTERRUPT_HARD && ((IS_M(env) && env->regs[15] < 0xfffffff0) || !(env->uncached_cpsr & CPSR_I))) { env->exception_index = EXCP_IRQ; do_interrupt(env); next_tb = 0; } do_interrupt() will be executed even if (env->uncached_cpsr & CPSR_I) == 1 , disable interrupt bit set. then changed to: if (interrupt_request & CPU_INTERRUPT_HARD && !(env->uncached_cpsr & CPSR_I) && (IS_M(env) ? env->regs[15] < 0xfffffff0: 1) ) { env->exception_index = EXCP_IRQ; do_interrupt(env); next_tb = 0; } works ** Affects: qemu Importance: Undecided Status: New ** Tags: arm cortexm -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/942659 Title: ARM: CORTEX M, PRIMASK does not disable interrupts Status in QEMU: New Bug description: qemu version 0.15.1 but the same code is in qemu 1.0 "CPSID I" does not disable interrupts for CORTEX M3 if (interrupt_request & CPU_INTERRUPT_HARD && ((IS_M(env) && env->regs[15] < 0xfffffff0) || !(env->uncached_cpsr & CPSR_I))) { env->exception_index = EXCP_IRQ; do_interrupt(env); next_tb = 0; } do_interrupt() will be executed even if (env->uncached_cpsr & CPSR_I) == 1 , disable interrupt bit set. then changed to: if (interrupt_request & CPU_INTERRUPT_HARD && !(env->uncached_cpsr & CPSR_I) && (IS_M(env) ? env->regs[15] < 0xfffffff0: 1) ) { env->exception_index = EXCP_IRQ; do_interrupt(env); next_tb = 0; } works To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/942659/+subscriptions