Currently the available PMU counters start at HPM3 and run through to the number specified by the "pmu-num" property. There is no requirement in the specification that the available counters be continously numbered. This series add suppport for specifying a discountinuous range of counters though a "pmu-mask" property.
Rob Bradford (3): target/riscv: Propagate error from PMU setup target/riscv: Support discontinuous PMU counters target/riscv: Don't assume PMU counters are continuous target/riscv/cpu.c | 9 ++++++++- target/riscv/cpu_cfg.h | 1 + target/riscv/csr.c | 5 +++-- target/riscv/pmu.c | 32 +++++++++++++++++++++----------- target/riscv/pmu.h | 3 ++- 5 files changed, 35 insertions(+), 15 deletions(-) -- 2.41.0
