Currently the available PMU counters start at HPM3 and run through to the number specified by the "pmu-num" property. There is no requirement in the specification that the available counters be continously numbered. This series add suppport for specifying a discountinuous range of counters though a "pmu-mask" property.
v2: * Use cfg.pmu_mask wherever cfg.pmu_num was used previously * Deprecate pmu_num property (warning, comment & updated documentation) * Override default pmu_mask value iff pmu_num changed from default Rob Bradford (6): target/riscv: Propagate error from PMU setup target/riscv: Don't assume PMU counters are continuous target/riscv: Use existing PMU counter mask in FDT generation qemu/bitops.h: Add MAKE_32BIT_MASK macro target/riscv: Add "pmu-mask" property to replace "pmu-num" docs/about/deprecated: Document RISC-V "pmu-num" deprecation docs/about/deprecated.rst | 10 ++++++++++ hw/riscv/virt.c | 2 +- include/qemu/bitops.h | 3 +++ target/riscv/cpu.c | 13 ++++++++++--- target/riscv/cpu_cfg.h | 3 ++- target/riscv/csr.c | 5 +++-- target/riscv/machine.c | 2 +- target/riscv/pmu.c | 35 +++++++++++++++++------------------ target/riscv/pmu.h | 5 +++-- 9 files changed, 50 insertions(+), 28 deletions(-) -- 2.41.0
