In preparation of raising -Wimplicit-fallthrough to 5, replace all
fall-through comments with the fallthrough attribute pseudo-keyword.
Reviewed-by: Cédric Le Goater <c...@kaod.org>
Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidiana...@linaro.org>
---
target/ppc/cpu_init.c | 8 ++++----
target/ppc/excp_helper.c | 6 +++---
target/ppc/mmu-radix64.c | 6 +++---
target/ppc/mmu_common.c | 12 ++++++------
target/ppc/translate.c | 6 +++---
5 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 40fe14a6c2..7a7bd4d824 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -894,25 +894,25 @@ static void register_BookE206_sprs(CPUPPCState *env,
uint32_t mas_mask,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
tlbncfg[3]);
- /* Fallthru */
+ fallthrough;
case 3:
spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
tlbncfg[2]);
- /* Fallthru */
+ fallthrough;
case 2:
spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
tlbncfg[1]);
- /* Fallthru */
+ fallthrough;
case 1:
spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
tlbncfg[0]);
- /* Fallthru */
+ fallthrough;
case 0:
default:
break;
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 7926114d5c..b8be34051c 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1334,7 +1334,7 @@ static bool is_prefix_insn_excp(PowerPCCPU *cpu, int excp)
*/
break;
}
- /* fall through */
+ fallthrough;
case POWERPC_EXCP_MCHECK:
case POWERPC_EXCP_DSI:
case POWERPC_EXCP_DSEG:
@@ -1576,7 +1576,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_TRACE: /* Trace exception */
msr |= env->error_code;
- /* fall through */
+ fallthrough;
case POWERPC_EXCP_DSEG: /* Data segment exception */
case POWERPC_EXCP_ISEG: /* Instruction segment exception */
case POWERPC_EXCP_SDOOR: /* Doorbell interrupt */
@@ -1584,7 +1584,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
msr |= env->error_code;
- /* fall through */
+ fallthrough;
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 5823e039e6..a85bd614bf 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -126,7 +126,7 @@ static void ppc_radix64_raise_si(PowerPCCPU *cpu,
MMUAccessType access_type,
break;
case MMU_DATA_STORE:
cause |= DSISR_ISSTORE;
- /* fall through */
+ fallthrough;
case MMU_DATA_LOAD:
/* Data Storage Interrupt */
cs->exception_index = POWERPC_EXCP_DSI;
@@ -166,7 +166,7 @@ static void ppc_radix64_raise_hsi(PowerPCCPU *cpu,
MMUAccessType access_type,
break;
case MMU_DATA_STORE:
cause |= DSISR_ISSTORE;
- /* fall through */
+ fallthrough;
case MMU_DATA_LOAD:
/* H Data Storage Interrupt */
cs->exception_index = POWERPC_EXCP_HDSI;
@@ -226,7 +226,7 @@ static int ppc_radix64_check_rc(MMUAccessType access_type,
uint64_t pte)
if (!(pte & R_PTE_C)) {
break;
}
- /* fall through */
+ fallthrough;
case MMU_INST_FETCH:
case MMU_DATA_LOAD:
if (!(pte & R_PTE_R)) {
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 6ca5d12207..dd44befe6f 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -76,7 +76,7 @@ static int pp_check(int key, int pp, int nx)
case 0x1:
case 0x2:
access |= PAGE_WRITE;
- /* fall through */
+ fallthrough;
case 0x3:
access |= PAGE_READ;
break;
@@ -559,7 +559,7 @@ static int mmu40x_get_physical_address(CPUPPCState *env,
mmu_ctx_t *ctx,
if (pr != 0) {
goto check_perms;
}
- /* fall through */
+ fallthrough;
case 0x3:
/* All accesses granted */
ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -573,7 +573,7 @@ static int mmu40x_get_physical_address(CPUPPCState *env,
mmu_ctx_t *ctx,
ret = -2;
break;
}
- /* fall through */
+ fallthrough;
case 0x1:
check_perms:
/* Check from TLB entry */
@@ -1349,7 +1349,7 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
break;
case POWERPC_MMU_BOOKE206:
booke206_update_mas_tlb_miss(env, eaddr, 2, mmu_idx);
- /* fall through */
+ fallthrough;
case POWERPC_MMU_BOOKE:
cs->exception_index = POWERPC_EXCP_ITLB;
env->error_code = 0;
@@ -1435,7 +1435,7 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr,
cpu_abort(cs, "MPC8xx MMU model is not implemented\n");
case POWERPC_MMU_BOOKE206:
booke206_update_mas_tlb_miss(env, eaddr, access_type,
mmu_idx);
- /* fall through */
+ fallthrough;
case POWERPC_MMU_BOOKE:
cs->exception_index = POWERPC_EXCP_DTLB;
env->error_code = 0;
@@ -1530,7 +1530,7 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr,
MMUAccessType access_type,
return ppc_radix64_xlate(cpu, eaddr, access_type, raddrp,
psizep, protp, mmu_idx, guest_visible);
}
- /* fall through */
+ fallthrough;
case POWERPC_MMU_64B:
case POWERPC_MMU_2_03:
case POWERPC_MMU_2_06:
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 329da4d518..a67b77258d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7472,10 +7472,10 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cs)
tcg_gen_exit_tb(ctx->base.tb, 0);
break;
}
- /* fall through */
+ fallthrough;
case DISAS_CHAIN_UPDATE:
gen_update_nip(ctx, nip);
- /* fall through */
+ fallthrough;
case DISAS_CHAIN:
/*
* tcg_gen_lookup_and_goto_ptr will exit the TB if
@@ -7490,7 +7490,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cs)
case DISAS_EXIT_UPDATE:
gen_update_nip(ctx, nip);
- /* fall through */
+ fallthrough;
case DISAS_EXIT:
pmu_count_insns(ctx);
tcg_gen_exit_tb(NULL, 0);
--
2.39.2
