This includes: - implementing SHA and CMPccXADD instruction extensions
- introducing a new mechanism for flags writeback that avoids a tricky failure - converting the more orthogonal parts of the one-byte opcode map, as well as the CMOVcc and SETcc instructions. Tested by booting several 32-bit and 64-bit guests. Paolo Paolo Bonzini (18): target/i386: group common checks in the decoding phase target/i386: validate VEX.W for AVX instructions target/i386: implement SHA instructions tests/tcg/i386: initialize more registers in test-avx tests/tcg/i386: test-avx: add test cases for SHA new instructions target/i386: accept full MemOp in gen_ext_tl target/i386: introduce flags writeback mechanism target/i386: implement CMPccXADD target/i386: do not clobber A0 in POP translation target/i386: reintroduce debugging mechanism target/i386: move 00-5F opcodes to new decoder target/i386: adjust decoding of J operand target/i386: split eflags computation out of gen_compute_eflags target/i386: move 60-BF opcodes to new decoder target/i386: move operand load and writeback out of gen_cmovcc1 target/i386: move remaining conditional operations to new decoder target/i386: remove now converted opcodes from old decoder target/i386: remove gen_op target/i386/cpu.c | 4 +- target/i386/ops_sse.h | 128 ++++ target/i386/tcg/decode-new.c.inc | 605 ++++++++++++++-- target/i386/tcg/decode-new.h | 41 +- target/i386/tcg/emit.c.inc | 726 ++++++++++++++++++- target/i386/tcg/ops_sse_header.h.inc | 14 + target/i386/tcg/translate.c | 1001 +++----------------------- tests/tcg/i386/Makefile.target | 2 +- tests/tcg/i386/test-avx.c | 8 + tests/tcg/i386/test-avx.py | 3 +- tests/tcg/i386/test-flags.c | 37 + 11 files changed, 1593 insertions(+), 976 deletions(-) create mode 100644 tests/tcg/i386/test-flags.c -- 2.41.0
