On 2024-08-13 18:43, Peter Maydell wrote:
On Tue, 13 Aug 2024 at 16:54, Jakob Bohm via <qemu-discuss@nongnu.org> wrote:
Another approach that might be worth examining would be to build the TCG
snippet collection for different host CPU generations (such as x86-64
with only SSE2, x86-64 with SSE3 and x86-64 with AVX512), thereby
providing fast emulation of the latest on the new on the new and medium
CPU generations . This would imply some table selection logic in the
TCG initialization based on actual host and selected guest CPUs. This
idea is mostly for Qemu binaries that will run on different hosts .
What "TCG snippet collection" ? QEMU generates code from IR
instruction-at-a-time, it doesn't do assembly of prebuilt
larger bits of code.
I was referring to the part of the old Qemu build process that compiles
a bunch of TCG equivalents, at least when the host CPU has no hardcoded
translations for the guest CPU.
We do have some support for runtime detection of host
CPU features, so we can generate better code if some
things are available; notably we will check for and
use AVX1, AVX2, AVX512 if available.
This seems to leave out the cases of SSE3 orig on x86-64
and SSE on 80386SX .
Enjoy
Jakob
--
Jakob Bohm, CIO, Partner, WiseMo A/S. https://www.wisemo.com
Transformervej 29, 2860 Søborg, Denmark. Direct +45 31 13 16 10
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