Terje Mathisen <[EMAIL PROTECTED]> writes:
> The next step is to build a 10 MHz (or faster!) counter which will
> reset on each PPS signal, then count until latched by a read signal
> from the NTP server. This allows you to get rid of the variable
> interrupt latency problem.
I'd be tempted to do it the other way around - have the counter
free-running and latch the count on each PPS. That way missed PPS
events (as unlikely as they are) wouldn't mean a slipped clock and
fractional counts wouldn't be lost. One could also read the clock at
any time and apply the scaling and offset to get the current precise
time.
I am still hoping that at one point the GPS-on-a-chip manufacturers
will provide a fast/painless way to read the GPS chip's internal
counter and correction factors via the chip's external bus.
This gps chip below is used in <$100 consumer gps's. With a bit of
cooperation from the company it should be possible to put it on a pci
card with a PCI-to-ARM bus coupler. (Or maybe PCI-e, because it uses
fewer pins?)
http://www.sirf.com/Downloads/Collateral/GSC3(f)_6.20.05.pdf
-wolfgang
--
Wolfgang S. Rupprecht http://www.wsrcc.com/wolfgang/
Direct SIP URL Dialing: http://www.wsrcc.com/wolfgang/phonedirectory.html
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