Augustine wrote: > On Mar 12, 3:59 am, Martin Burnicki <martin.burni...@meinberg.de> > wrote: >> >> Do you have some pointers where this is explained? > > Perhaps, suffice to look at page 252 and 293 of > http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/40546.pdf > where you can find the formula to calculate the latency for RDTSC on > Phenom processors. Also page B-5 of > http://download.intel.com/design/processor/manuals/248966.pdf, where it > states that the precision of RDTSC on Intel processors is 64 CPU clock > cycles, and page C-29, where the latency is shown. > > In both documents, several events that may cause the TSC to get out of > sync with time are also mentioned. That's why the TSC has been > abandoned as a time source in recent kernels in favor of the PM timer > and HPET or even the PIT.
Great! Thanks for the pointer. Martin -- Martin Burnicki Meinberg Funkuhren Bad Pyrmont Germany _______________________________________________ questions mailing list questions@lists.ntp.org https://lists.ntp.org/mailman/listinfo/questions
