On Thu, Dec 13, 2012 at 08:23:47AM -0500, Brian Utterback wrote: > >The internal clock of the network controller is the PHC for IEEE1588, > >it has a 1 ns resolution, and can be steered with a 32 bit fractional > >of 1 ns. see SYSTIML and TIMINCA in the I210 datasheet. > > > >// jwalck > > I know that. The problem is that there is going to be jitter > introduced when you set the clock from the kernel. That is generally > the problem with IEEE 1588, getting the time from the controller to > the kernel and vice versa. If you have to go across a PCI bus for > instance that will introduce jitter.
>From what I have seen, with multiple readings and some filtering, the jitter is very small, somewhere in nanoseconds or couple tens of nanoseconds. Even if the delay was highly asymmetric, with 2us RTT the error would be only 1 us, which is still much better than the delays causing the error in the TX timestamp on Ethernet. The phc2sys program from the linuxptp project can be used to synchronize the system clock to the PHC or the PHC to the system clock. It can do that via PPS or filtered clock readings. -- Miroslav Lichvar _______________________________________________ questions mailing list questions@lists.ntp.org http://lists.ntp.org/listinfo/questions
