I think the best way to implement what you describe for a "better version" is as follows:
Expand `(instance h1 half-adder-arch)` into something like (define-syntax h1 (half-adder-arch-info)) Where `half-adder-arch-info` is an expansion-time structure describing half-adders. Then the `assign` macro can use `syntax-local-value` to get out that information, see that it's a half-adder, and then generate the code you've written manually. This paper: https://arxiv.org/abs/1106.2578 talks about this technique in more detail, focused on the implementation of `match-expander`s, which work this way, but it's a common Racket technique and used for structs, syntax classes, `for` transformers, and more. Sam ( On Tue, May 26, 2020 at 3:08 PM Guillaume Savaton <guillaume.sava...@gmail.com> wrote: > > Le mardi 26 mai 2020 03:59:59 UTC+2, johnbclements a écrit : >> >> > So far, I have made two attempts to work around these issues: (1) by >> > creating a metamodel-like data structure using Racket structs, and >> > transforming syntax objects into struct instances; or (2) using syntax >> > objects only and attaching context data to each of them as a syntax >> > property. >> > Both have strengths and weaknesses, and I am still feeling that I am not >> > using Racket with the right mindset. >> >> I think your (2) sounds like a lighter-weight solution. However, it >> definitely does seem as though much of the difficulty here is related to the >> differences between a more imperative and a more functional style. > > > I'm not sure that solution (2) is lighter. Maybe the weight is moved to > another part of the implementation :) > > I have set up an example at this address: > https://gist.github.com/senshu/c6db95615b4b2567f168d6bfbe61655e > > It is basically a very stripped-down hardware description language that > borrows from VHDL and Verilog. > Like VHDL, the description of a circuit is split into an "entity" (the > interface of the circuit) and an "architecture" (the implementation). > For the sake of simplicity, this example does not implement a complete model > of computation. > > The file "tiny-hdl-example-v1.rkt" implements a full adder and prints its > truth table. > At this point, there is no name resolution, so I need to give redundant > information in the "port-ref" expressions. > A better version of the language would allow to write: > > (assign (h1 a) a) > > instead of: > > (assign (port-ref half-adder h1 a) (port-ref full-adder a)) > > because we know that > > h1 is an instance of half-adder-arch, that has the entity half-adder, > the current architecture is full-adder-arch and its entity is full-adder > > I hope it clarifies my current concerns. > > Guillaume > > -- > You received this message because you are subscribed to the Google Groups > "Racket Users" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to racket-users+unsubscr...@googlegroups.com. > To view this discussion on the web visit > https://groups.google.com/d/msgid/racket-users/a42ec2de-6441-483f-a05a-910c03c317e8%40googlegroups.com. -- You received this message because you are subscribed to the Google Groups "Racket Users" group. To unsubscribe from this group and stop receiving emails from it, send an email to racket-users+unsubscr...@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/racket-users/CAK%3DHD%2BYs2_w3JtDb5mDDWOtqswXjcGo34hVmHiucDUihnZbbWw%40mail.gmail.com.
