Align the order of two MFC clocks with Exynos4 DTS and MFC bindings
Link: https://lore.kernel.org/r/20230328114729.61436-1-aakarsh.j...@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlow...@linaro.org>
---
arch/arm/boot/dts/s5pv210.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi
index fbe7f3d17f41..d9436bbf77c8 100644
--- a/arch/arm/boot/dts/s5pv210.dtsi
+++ b/arch/arm/boot/dts/s5pv210.dtsi
@@ -452,8 +452,8 @@ mfc: codec@f1700000 {
reg = <0xf1700000 0x10000>;
interrupt-parent = <&vic2>;
interrupts = <14>;
- clocks = <&clocks DOUT_MFC>, <&clocks CLK_MFC>;
- clock-names = "sclk_mfc", "mfc";
+ clocks = <&clocks CLK_MFC>, <&clocks DOUT_MFC>;
+ clock-names = "mfc", "sclk_mfc";
};
vic0: interrupt-controller@f2000000 {
--
2.34.1
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