Author: sginsberg
Date: Mon Mar 26 14:51:03 2012
New Revision: 56237
URL: http://svn.reactos.org/svn/reactos?rev=56237&view=rev
Log:
- Revert hack.
Modified:
trunk/reactos/hal/halx86/up/pic.c
Modified: trunk/reactos/hal/halx86/up/pic.c
URL:
http://svn.reactos.org/svn/reactos/trunk/reactos/hal/halx86/up/pic.c?rev=56237&r1=56236&r2=56237&view=diff
==============================================================================
--- trunk/reactos/hal/halx86/up/pic.c [iso-8859-1] (original)
+++ trunk/reactos/hal/halx86/up/pic.c [iso-8859-1] Mon Mar 26 14:51:03 2012
@@ -666,29 +666,25 @@
/* Set old IRQL */
Pcr->Irql = OldIrql;
- /* Make sure interrupts were enabled */
- if (EFlags & EFLAGS_INTERRUPT_MASK)
- {
- /* Check for pending software interrupts and compare with current IRQL
*/
- PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql];
- if (PendingIrqlMask)
+ /* Check for pending software interrupts and compare with current IRQL */
+ PendingIrqlMask = Pcr->IRR & FindHigherIrqlMask[OldIrql];
+ if (PendingIrqlMask)
+ {
+ /* Check if pending IRQL affects hardware state */
+ BitScanReverse(&PendingIrql, PendingIrqlMask);
+ if (PendingIrql > DISPATCH_LEVEL)
{
- /* Check if pending IRQL affects hardware state */
- BitScanReverse(&PendingIrql, PendingIrqlMask);
- if (PendingIrql > DISPATCH_LEVEL)
- {
- /* Set new PIC mask */
- Mask.Both = Pcr->IDR & 0xFFFF;
- __outbyte(PIC1_DATA_PORT, Mask.Master);
- __outbyte(PIC2_DATA_PORT, Mask.Slave);
-
- /* Clear IRR bit */
- Pcr->IRR ^= (1 << PendingIrql);
- }
-
- /* Now handle pending interrupt */
- SWInterruptHandlerTable[PendingIrql]();
+ /* Set new PIC mask */
+ Mask.Both = Pcr->IDR & 0xFFFF;
+ __outbyte(PIC1_DATA_PORT, Mask.Master);
+ __outbyte(PIC2_DATA_PORT, Mask.Slave);
+
+ /* Clear IRR bit */
+ Pcr->IRR ^= (1 << PendingIrql);
}
+
+ /* Now handle pending interrupt */
+ SWInterruptHandlerTable[PendingIrql]();
}
/* Restore interrupt state */
