[rtc-linux] Design Verification Engineer

[Ankit Gautam]

Hi ,

 Hope everyone having a good time!!

 I have an exciting job opportunity.

 

Role- Design Verification Engineer

Work Location: Santa Clara, CA

Duration: Long term contract

Immediate Interview

 

Experience:

Skills: UVM/System verilog, cadence tools, VCS tools, using and integrating VIP, above mentioned protocols experience , GLS bring up and debug and other standard DV experience of creating TB and testcase. Good to have some real number modeling of analog designs in SystemVerilog, not mandatory.

UVM/System verilog, cadence tools, VCS tools, using and integrating VIP, above mentioned protocols experience , GLS bring up and debug and other standard DV experience of creating TB and testcase. Good to have some real number modeling of analog designs in SystemVerilog, not mandatory.

 

Regards;

Ankit Gautam

+1 (678-659-9420)

ankit.gau...@expediteinc.com

Expedite Technology Solutions, LLC│11785 Northfall Lane, Alpharetta, GA - 30009

If you would prefer to no longer receive any emails from this Company, you may opt out at anytime by clicking unsubscribe.

--
You received this message because you are subscribed to "rtc-linux".
Membership options at http://groups.google.com/group/rtc-linux .
Please read http://groups.google.com/group/rtc-linux/web/checklist
before submitting a driver.
---
You received this message because you are subscribed to the Google Groups "rtc-linux" group.
To unsubscribe from this group and stop receiving emails from it, send an email to rtc-linux+unsubscr...@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/rtc-linux/1353391232.9575.1707406497939%40emailmerge24.jobdiva.com.