On 08/14/13 04:22 PM, Sebastian Huber wrote:
On 2013-08-14 15:36, Karel Gardas wrote:
diff --git a/c/src/lib/libbsp/arm/lm3s69xx/startup/bspstart.c
b/c/src/lib/libbsp/arm/lm3s69xx/startup/bspstart.c
index 442c713..170b54e 100644
--- a/c/src/lib/libbsp/arm/lm3s69xx/startup/bspstart.c
+++ b/c/src/lib/libbsp/arm/lm3s69xx/startup/bspstart.c
@@ -19,32 +19,65 @@ static void init_main_osc(void)
volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;

uint32_t sysdiv_val = LM3S69XX_PLL_FREQUENCY / LM3S69XX_SYSTEM_CLOCK;
+#if defined(LM3S69XX_MCU_LM3S6965) || defined(LM3S69XX_MCU_LM3S3749)
assert(sysdiv_val * LM3S69XX_SYSTEM_CLOCK == LM3S69XX_PLL_FREQUENCY);
+#endif
assert((sysdiv_val >= 4) && (sysdiv_val <= 16));

uint32_t rcc = syscon->rcc;
+ uint32_t rcc2 = syscon->rcc2;

Will this syscon->rcc2 stuff work on the other LM3SXXXX chips?

It should. I've done my best to read LM3S6965, LM3S3749 and my LM4F120H5QR and compare and it looks like RCC2 is supported on both older chips. I would not need to use RCC2 if I would be satisfied with 50MHz speed, but since chip support 80 MHz, I needed to enter RCC2/DIV400/ land.

What makes me more nervous about supporting older chips is addition:

  rcc &= SYSCONRCC_MOSCDIS;
  syscon->rcc = rcc;

^ w/o this my code is not running at all, i.e. it probably runs on default 12 MHz. I'm curious how older chips worked without this. I've also added various waits as recommended and as used in TI's own StellarisWare library. This is needed as in chip spec., itself, there are no such details provided... :-(

BTW: the code in question is a result of a code merge, since in original version I've had an #ifdef block of code supporting old LM3S* and another #ifdef for LM4F*, but later I've decided to merge both codes together. If you prefer former code form just let me know and I can resurrect it from my backups...

Thanks for review.
Karel
PS: I'm sorry but due to not having any LM3S board I'm not able to test former chips BSP support on real hardware...
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