Hello,
I was quite busy with SMP changes in the last couple of weeks. Here is a
status report:
- SMP port to PowerPC and ARM.
- Simplification of low-level start.
- Usage of not available features will return an error status. See also
+smptests/smpunsupported01+.
- CPU architecture specific SMP lock API. See also +smptests/smplock01+.
- ISR locks (used by TOD handler, Termios, file system).
- Cache optimized per-CPU controls leading to better performance and easier
assembler code.
- Per-CPU thread dispatch disable level. This is a huge performance
improvement. It greatly simplifies the interrupt entry/exit assembler code.
This fixed the '_Thread_Dispatch()' bug of missed thread dispatch necessary
indications (see +sptests/spintrcritical18+) and also PR2082.
- Useful test results with RTEMS debug enabled.
- RTEMS debug controlled assertions, see also '_Assert()'. Now this can be
used effectively since the test suite yields useful results with RTEMS_DEBUG
enabled.
- Systematic bug prevention with RTEMS asserts, see also '_Per_CPU_Get()'.
- Two G-FP scheduler implementations and general SMP support for the
scheduler. See also +smptests/smpscheduler01+, +smptests/smpmigration01+ and
+smptesets/smpswitchextension01+.
- Header file re-organization to reduce the dependencies between source and
header files. This simplifies code review and reduces build times during
development. See also PR766.
The test suite with SMP and debug enabled yields good results on ARM and
PowerPC.
The next major issue is the ISR disable/enable used for mutual exclusion. This
will not longer work on SMP.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : [email protected]
PGP : Public key available on request.
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
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