These patches create a new BSP for the Alteras Cyclone-V.
This BSP supports SMP on two cores.
It uses a new libchip driver for the Synopsys IP DWMAC 1000
onchip network controller.
It suuports the L2C-310 level 2 cache controller from arm in
arm/shared/arm-l2c-310/cache_.h.
In addition the general level 1 cache handling for the arm level 1
cache controller has been separated to /arm/include/arm-cache-l1.h.
With arm/include/arm-errata.h and arm/include/arm-release-id.h it
also supports a basic errata handling which was required for
implementing the L2C-310 level 2 cache.
Patches 1 - 4 do preparation work for the BSP
Patches 5 - 9 add the basic arrata handling.
Patch 10 partially applies one of the erratas which is required
for the L2 cache handling
Patches 11 - 12 implement the cache handling and share it with the
xilinx-zynq BSP
Patch 13 Adds the Synopsys IP DWMAC 1000 network driver as a
libchip driver
Patches 14 - 17 Implement the new BSP for Alteras Cyclone-V
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