The previous implementation used an instruction cache line size of 0,
this is a bogus value. Use a instruction cache line size of 64 since
the L2 cache may have a line size of 32 or 64. A greater value should
cause no harm.
Use a FLUSH operation for _CPU_cache_invalidate_instruction_range().
This is a preperation step to support the L2 cache.
---
c/src/lib/libbsp/sparc/leon3/Makefile.am | 6 +-
c/src/lib/libbsp/sparc/leon3/include/cache_.h | 109 +++++++++++++++++++++++++
2 files changed, 114 insertions(+), 1 deletions(-)
create mode 100644 c/src/lib/libbsp/sparc/leon3/include/cache_.h
diff --git a/c/src/lib/libbsp/sparc/leon3/Makefile.am
b/c/src/lib/libbsp/sparc/leon3/Makefile.am
index 5134b34..a9b8def 100644
--- a/c/src/lib/libbsp/sparc/leon3/Makefile.am
+++ b/c/src/lib/libbsp/sparc/leon3/Makefile.am
@@ -117,6 +117,11 @@ libbsp_a_SOURCES += ../../sparc/shared/i2c/i2cmst.c
# timer
libbsp_a_SOURCES += timer/timer.c
+# Cache
+libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += include/cache_.h
+libbsp_a_CPPFLAGS = -I$(srcdir)/include
+
if HAS_SMP
libbsp_a_SOURCES += smp/smp_leon3.c
endif
@@ -154,7 +159,6 @@ endif
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/access.rel \
- ../../../libcpu/@RTEMS_CPU@/cache.rel \
../../../libcpu/@RTEMS_CPU@/reg_win.rel \
../../../libcpu/@RTEMS_CPU@/syscall.rel
diff --git a/c/src/lib/libbsp/sparc/leon3/include/cache_.h
b/c/src/lib/libbsp/sparc/leon3/include/cache_.h
new file mode 100644
index 0000000..eafbb48
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/leon3/include/cache_.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2014 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Dornierstr. 4
+ * 82178 Puchheim
+ * Germany
+ * <rt...@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LEON3_CACHE_H
+#define LEON3_CACHE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
+
+#define CPU_INSTRUCTION_CACHE_ALIGNMENT 64
+
+static inline void _CPU_cache_flush_data_range(
+ const void *d_addr,
+ size_t n_bytes
+)
+{
+ /* TODO */
+}
+
+static inline void _CPU_cache_invalidate_data_range(
+ const void *d_addr,
+ size_t n_bytes
+)
+{
+ /* TODO */
+}
+
+static inline void _CPU_cache_freeze_data(void)
+{
+ /* TODO */
+}
+
+static inline void _CPU_cache_unfreeze_data(void)
+{
+ /* TODO */
+}
+
+static inline void _CPU_cache_invalidate_entire_instruction(void)
+{
+ __asm__ volatile ("flush");
+}
+
+static inline void _CPU_cache_invalidate_instruction_range(
+ const void *i_addr,
+ size_t n_bytes
+)
+{
+ _CPU_cache_invalidate_entire_instruction();
+}
+
+static inline void _CPU_cache_freeze_instruction(void)
+{
+ /* TODO */
+}
+
+static inline void _CPU_cache_unfreeze_instruction(void)
+{
+ /* TODO */
+}
+
+static inline void _CPU_cache_flush_entire_data(void)
+{
+ /* TODO */
+}
+
+static inline void _CPU_cache_invalidate_entire_data(void)
+{
+ /* TODO */
+}
+
+static inline void _CPU_cache_enable_data(void)
+{
+ /* TODO */
+}
+
+static inline void _CPU_cache_disable_data(void)
+{
+ /* TODO */
+}
+
+static inline void _CPU_cache_enable_instruction(void)
+{
+ /* TODO */
+}
+
+static inline void _CPU_cache_disable_instruction(void)
+{
+ /* TODO */
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LEON3_CACHE_H */
--
1.7.7
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