On Wed, Feb 26, 2014 at 5:51 AM, Ralf Kirchner <ralf.kirch...@embedded-brains.de> wrote: > --- > c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h | 12 ++++++++++++ > c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h | 10 ++++++++++ > 2 Dateien geändert, 22 Zeilen hinzugefügt(+) > > diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h > b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h > index 0910e4c..28640d2 100644 > --- a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h > +++ b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h > @@ -46,6 +46,18 @@ typedef struct { > #define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, > 8, 15) > uint32_t pwrst; > uint32_t invss; > +#define A9MPCORE_SCU_INVSS_CPU0(ways) BSP_FLD32(val, 0, 3) > +#define A9MPCORE_SCU_INVSS_CPU0_GET(reg) /* Write only register */ > +#define A9MPCORE_SCU_INVSS_CPU0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) > +#define A9MPCORE_SCU_INVSS_CPU1(ways) BSP_FLD32(val, 4, 7) > +#define A9MPCORE_SCU_INVSS_CPU1_GET(reg) /* Write only register */ > +#define A9MPCORE_SCU_INVSS_CPU1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) > +#define A9MPCORE_SCU_INVSS_CPU2(ways) BSP_FLD32(val, 8, 11) > +#define A9MPCORE_SCU_INVSS_CPU2_GET(reg) /* Write only register */ > +#define A9MPCORE_SCU_INVSS_CPU2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) > +#define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15) > +#define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */ > +#define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) > uint32_t reserved_10[12]; > uint32_t fltstart; > uint32_t fltend; > diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h > b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h > index dd1b7c1..ad4cf42 100644 > --- a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h > +++ b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h > @@ -70,6 +70,13 @@ BSP_START_TEXT_SECTION static inline > arm_a9mpcore_start_set_vector_base(void) > } > } > > +BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_scu_invalidate(const > uint32_t cpu_id, const uint32_t ways) > +{ > + volatile a9mpcore_scu *scu = (volatile a9mpcore_scu *) > BSP_ARM_A9MPCORE_SCU_BASE; > + > + scu->invss = ( ( ways & 0xF ) << ( ( cpu_id & 0x3 ) * 4 ) ); > +} why masking ways and cpu_id? can ways ever be more than 15? if > 3 cpus will this work right?
> + > BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_0(void) > { > #ifdef RTEMS_SMP > @@ -86,6 +93,9 @@ BSP_START_TEXT_SECTION static inline > arm_a9mpcore_start_hook_0(void) > arm_cp15_set_auxiliary_control(actlr); > > cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id(); > + > + arm_a9mpcore_start_scu_invalidate(cpu_id, 0xF); > + > if (cpu_id != 0) { > arm_a9mpcore_start_set_vector_base(); > > -- > 1.7.10.4 > > _______________________________________________ > rtems-devel mailing list > rtems-devel@rtems.org > http://www.rtems.org/mailman/listinfo/rtems-devel _______________________________________________ rtems-devel mailing list rtems-devel@rtems.org http://www.rtems.org/mailman/listinfo/rtems-devel