Made Alteras hwlib compile clean within the RTEMS build system --- c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 1 + .../altera-cyclone-v/hwlib/include/socal/socal.h | 4 +- .../hwlib/src/hwmgr/alt_clock_manager.c | 282 +------------------- 3 Dateien geändert, 6 Zeilen hinzugefügt(+), 281 Zeilen entfernt(-)
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index e552f23..6b1749b 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -98,6 +98,7 @@ libbsp_a_LIBADD = # for the Altera hwlib libbsp_a_CPPFLAGS += -I ${srcdir}/hwlib/include libbsp_a_CPPFLAGS += -std=gnu99 +CFLAGS += -Wno-missing-prototypes # hwlib from Altera libbsp_a_SOURCES += hwlib/src/hwmgr/alt_16550_uart.c diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h index d1a876c..b0375e5 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/include/socal/socal.h @@ -33,6 +33,8 @@ #ifndef __ALTERA_SOCAL_H__ #define __ALTERA_SOCAL_H__ +#include <rtems/score/basedefs.h> + #ifdef __cplusplus extern "C" { @@ -344,7 +346,7 @@ typedef char alt_cat_compile_assert_text(assertion_at_##file##_line_, line)[2*!! * \param a - Structure to be evaluated * \param b - Reference size */ -#define alt_check_struct_size(a, b) alt_form_compile_assert_line((sizeof(a) <= sizeof(b)),__FILE__,__LINE__) +#define alt_check_struct_size(a, b) RTEMS_STATIC_ASSERT((sizeof(a) <= sizeof(b)), Invalid_stuct_size) /*! @} */ diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c index ce01ff7..c731ad3 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/hwlib/src/hwmgr/alt_clock_manager.c @@ -225,7 +225,7 @@ static void inline alt_clk_mgr_wait(void* reg, uint32_t cnt) // to zero and allow for writing a new divisor ratio to it -ALT_STATUS_CODE alt_clk_plls_settle_wait(void) +static ALT_STATUS_CODE alt_clk_plls_settle_wait(void) { int32_t i = ALT_BYPASS_TIMEOUT_CNT; bool nofini; @@ -734,7 +734,7 @@ ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll) /* alt_clk_pll_source_get() returns the current input of the specified PLL. */ /****************************************************************************************/ -ALT_CLK_t alt_clk_pll_source_get(ALT_CLK_t pll) +static ALT_CLK_t alt_clk_pll_source_get(ALT_CLK_t pll) { ALT_CLK_t ret = ALT_CLK_UNKNOWN; uint32_t temp; @@ -4928,281 +4928,3 @@ ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_gro if (byp) { ret = alt_clk_pll_bypass_disable(pll); } return ret; } - - - -/****************************************************************************************/ -/* alt_clk_id_to_string() converts a clock ID to a text string. */ -/****************************************************************************************/ - - -ALT_STATUS_CODE alt_clk_id_to_string(ALT_CLK_t clk_id, char *s, size_t num) -{ - ALT_STATUS_CODE ret = ALT_E_ERROR; - uint32_t num2; - char *t = NULL; - - if (s != NULL) - { - s[0] = '\0'; - switch (clk_id) - { - case ALT_CLK_IN_PIN_OSC1: - t = "ALT_CLK_IN_PIN_OSC1"; - break; - case ALT_CLK_IN_PIN_OSC2: - t = "ALT_CLK_IN_PIN_OSC2"; - break; - - /* FPGA Clock Sources External to HPS */ - case ALT_CLK_F2H_PERIPH_REF: - t = "ALT_CLK_F2H_PERIPH_REF"; \ - break; - case ALT_CLK_F2H_SDRAM_REF: - t = "ALT_CLK_F2H_SDRAM_REF"; - break; - - /* Other Clock Sources External to HPS */ - case ALT_CLK_IN_PIN_JTAG: - t = "ALT_CLK_IN_PIN_JTAG"; - break; - case ALT_CLK_IN_PIN_ULPI0: - t = "ALT_CLK_IN_PIN_ULPI0"; - break; - case ALT_CLK_IN_PIN_ULPI1: - t = "ALT_CLK_IN_PIN_ULPI1"; - break; - case ALT_CLK_IN_PIN_EMAC0_RX: - t = "ALT_CLK_IN_PIN_EMAC0_RX"; - break; - case ALT_CLK_IN_PIN_EMAC1_RX: - t = "ALT_CLK_IN_PIN_EMAC1_RX"; - break; - - /* PLLs */ - case ALT_CLK_MAIN_PLL: - t = "ALT_CLK_MAIN_PLL"; - break; - case ALT_CLK_PERIPHERAL_PLL: - t = "ALT_CLK_PERIPHERAL_PLL"; - break; - case ALT_CLK_SDRAM_PLL: - t = "ALT_CLK_SDRAM_PLL"; - break; - - /* OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived - * directly from the osc_clk_1_HPS pin */ - case ALT_CLK_OSC1: - t = "ALT_CLK_OSC1"; - break; - - /* Main Clock Group - The following clocks are derived from the Main PLL. */ - case ALT_CLK_MAIN_PLL_C0: - t = "ALT_CLK_MAIN_PLL_C0"; - break; - case ALT_CLK_MAIN_PLL_C1: - t = "ALT_CLK_MAIN_PLL_C1"; - break; - case ALT_CLK_MAIN_PLL_C2: - t = "ALT_CLK_MAIN_PLL_C2"; - break; - case ALT_CLK_MAIN_PLL_C3: - t = "ALT_CLK_MAIN_PLL_C3"; - break; - case ALT_CLK_MAIN_PLL_C4: - t = "ALT_CLK_MAIN_PLL_C4"; - break; - case ALT_CLK_MAIN_PLL_C5: - t = "ALT_CLK_MAIN_PLL_C5"; - break; - case ALT_CLK_MPU: - t = "ALT_CLK_MPU"; - break; - case ALT_CLK_MPU_L2_RAM: - t = "ALT_CLK_MPU_L2_RAM"; - break; - case ALT_CLK_MPU_PERIPH: - t = "ALT_CLK_MPU_PERIPH"; - break; - case ALT_CLK_L3_MAIN: - t = "ALT_CLK_L3_MAIN"; - break; - case ALT_CLK_L3_MP: - t = "ALT_CLK_L3_MP"; - break; - case ALT_CLK_L3_SP: - t = "ALT_CLK_L3_SP"; - break; - case ALT_CLK_L4_MAIN: - t = "ALT_CLK_L4_MAIN"; - break; - case ALT_CLK_L4_MP: - t = "ALT_CLK_L4_MP"; - break; - case ALT_CLK_L4_SP: - t = "ALT_CLK_L4_SP"; - break; - case ALT_CLK_DBG_BASE: - t = "ALT_CLK_DBG_BASE"; - break; - case ALT_CLK_DBG_AT: - t = "ALT_CLK_DBG_AT\0"; - break; - case ALT_CLK_DBG_TRACE: - t = "ALT_CLK_DBG_TRACE"; - break; - case ALT_CLK_DBG_TIMER: - t = "ALT_CLK_DBG_TIMER"; - break; - case ALT_CLK_DBG: - t = "ALT_CLK_DBG"; - break; - case ALT_CLK_MAIN_QSPI: - t = "ALT_CLK_MAIN_QSPI"; - break; - case ALT_CLK_MAIN_NAND_SDMMC: - t = "ALT_CLK_MAIN_NAND_SDMMC"; - break; - case ALT_CLK_CFG: - t = "ALT_CLK_CFG"; - break; - case ALT_CLK_H2F_USER0: - t = "ALT_CLK_H2F_USER0"; - break; - - /* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */ - case ALT_CLK_PERIPHERAL_PLL_C0: - t = "ALT_CLK_PERIPHERAL_PLL_C0"; - break; - case ALT_CLK_PERIPHERAL_PLL_C1: - t = "ALT_CLK_PERIPHERAL_PLL_C1"; - break; - case ALT_CLK_PERIPHERAL_PLL_C2: - t = "ALT_CLK_PERIPHERAL_PLL_C2"; - break; - case ALT_CLK_PERIPHERAL_PLL_C3: - t = "ALT_CLK_PERIPHERAL_PLL_C3"; - break; - case ALT_CLK_PERIPHERAL_PLL_C4: - t = "ALT_CLK_PERIPHERAL_PLL_C4"; - break; - case ALT_CLK_PERIPHERAL_PLL_C5: - t = "ALT_CLK_PERIPHERAL_PLL_C5"; - break; - case ALT_CLK_USB_MP: - t = "ALT_CLK_USB_MP"; - break; - case ALT_CLK_SPI_M: - t = "ALT_CLK_SPI_M"; - break; - case ALT_CLK_QSPI: - t = "ALT_CLK_QSPI"; - break; - case ALT_CLK_NAND_X: - t = "ALT_CLK_NAND_X"; - break; - case ALT_CLK_NAND: - t = "ALT_CLK_NAND"; - break; - case ALT_CLK_SDMMC: - t = "ALT_CLK_SDMMC"; - break; - case ALT_CLK_EMAC0: - t = "ALT_CLK_EMAC0"; - break; - case ALT_CLK_EMAC1: - t = "ALT_CLK_EMAC1"; - break; - case ALT_CLK_CAN0: - t = "ALT_CLK_CAN0"; - break; - case ALT_CLK_CAN1: - t = "ALT_CLK_CAN1"; - break; - case ALT_CLK_GPIO_DB: - t = "ALT_CLK_GPIO_DB"; - break; - case ALT_CLK_H2F_USER1: - t = "ALT_CLK_H2F_USER1"; - break; - - /* SDRAM Clock Group - The following clocks are derived from the SDRAM PLL */ - case ALT_CLK_SDRAM_PLL_C0: - t = "ALT_CLK_SDRAM_PLL_C0"; - break; - case ALT_CLK_SDRAM_PLL_C1: - t = "ALT_CLK_SDRAM_PLL_C1"; - break; - case ALT_CLK_SDRAM_PLL_C2: - t = "ALT_CLK_SDRAM_PLL_C2"; - break; - case ALT_CLK_SDRAM_PLL_C3: - t = "ALT_CLK_SDRAM_PLL_C3"; - break; - case ALT_CLK_SDRAM_PLL_C4: - t = "ALT_CLK_SDRAM_PLL_C4"; - break; - case ALT_CLK_SDRAM_PLL_C5: - t = "ALT_CLK_SDRAM_PLL_C5"; - break; - case ALT_CLK_DDR_DQS: - t = "ALT_CLK_DDR_DQS"; - break; - case ALT_CLK_DDR_2X_DQS: - t = "ALT_CLK_DDR_2X_DQS"; - break; - case ALT_CLK_DDR_DQ: - t = "ALT_CLK_DDR_DQ"; - break; - case ALT_CLK_H2F_USER2: - t = "ALT_CLK_H2F_USER2"; - break; - - /* Clock Output Pins */ - case ALT_CLK_OUT_PIN_EMAC0_TX: - t = "ALT_CLK_OUT_PIN_EMAC0_TX"; - break; - case ALT_CLK_OUT_PIN_EMAC1_TX: - t = "ALT_CLK_OUT_PIN_EMAC1_TX"; - break; - case ALT_CLK_OUT_PIN_SDMMC: - t = "ALT_CLK_OUT_PIN_SDMMC"; - break; - case ALT_CLK_OUT_PIN_I2C0_SCL: - t = "ALT_CLK_OUT_PIN_I2C0_SCL"; - break; - case ALT_CLK_OUT_PIN_I2C1_SCL: - t = "ALT_CLK_OUT_PIN_I2C1_SCL"; - break; - case ALT_CLK_OUT_PIN_I2C2_SCL: - t = "ALT_CLK_OUT_PIN_I2C2_SCL"; - break; - case ALT_CLK_OUT_PIN_I2C3_SCL: - t = "ALT_CLK_OUT_PIN_I2C3_SCL"; - break; - case ALT_CLK_OUT_PIN_SPIM0: - t = "ALT_CLK_OUT_PIN_SPIM0"; - break; - case ALT_CLK_OUT_PIN_SPIM1: - t = "ALT_CLK_OUT_PIN_SPIM1"; - break; - case ALT_CLK_OUT_PIN_QSPI: - t = "ALT_CLK_OUT_PIN_QSPI"; - break; - case ALT_CLK_UNKNOWN: - t = "ALT_CLK_UNKNOWN"; - break; - // do *not* put a 'default' statement here. Then the compiler will throw - // an error if another clock id enum is added if the corresponding - // string is not added to this function. - } - if (t != NULL) { - num2 = strlen(t) + 1; - if (num2 < num) { num = num2; } - strncpy(s, t, num); - if (s[0] != '\0') { ret = ALT_E_SUCCESS; } - } - } - return ret; -} - -- 1.7.10.4 _______________________________________________ rtems-devel mailing list rtems-devel@rtems.org http://www.rtems.org/mailman/listinfo/rtems-devel