Hello Chris, On 2014-05-01 19:53, Chris Nott wrote:
Just reviewing interrupts now. I'm not sure your question fully makes sense. Unlike smaller embedded arms (eg. Cortex-M3), he interrupts on Cortex-A8 are two-phase. There is an external (to the ARM core) interrupt controller that feeds interrupts to the ARM IRQ and FIRQ lines. The ARM process itself actually only has those two interrupt signals. It looks like the code currently handles IRQ and FIRQ serially, so any interrupts at each level would be handled serially regardless of priority set in the INTC. Presumably what we eventually want to do here for both IRQ and FIRQ handlers is, receive the interrupt, immediately set the INTC priority to the received interrupt level to block lower priority interrupts (including the current interrupt), then acknowledge IRQ/FIRQ and dispatch the actual interrupt handler at a lower CPU priority so we can nest IRQ/FIRQ and handle higher priority interrupts.
the FIRQ are not supported at the operating system level in RTEMS, see also comment in cpu.h.
I'm not quite familiar with ARM family yet to be sure how this is normally accomplished or if there is an existing supported ARM with the same interrupt controller structure. TI provide sample source including interrupt handler that supports this stuff. It might be a good place to start playing with it, the source pretty much compiles fine in the RTEMS environment.
The interrupt priority handling must be accomplished by the interrupt controller. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. _______________________________________________ rtems-devel mailing list rtems-devel@rtems.org http://www.rtems.org/mailman/listinfo/rtems-devel
