Here's the patch I mentioned that allows use of 8254 ch. 1
instead of ch. 2. This patch is against rtlinux 3.0pre8.
This patch works well on my AMD SC400 target; ch. 1 is not
required for DRAM refresh on this platform. YMMV.
- Jason Sodergren / [EMAIL PROTECTED]
Dearborn Group / 248-488-2080 x306
======================================= cut here ========================
diff -u -r rtlinux-3.0_orig/schedulers/i386/rtl_time.c
rtlinux-3.0/schedulers/i386/rtl_time.c
--- rtlinux-3.0_orig/schedulers/i386/rtl_time.c Sun Oct 1 13:08:52 2000
+++ rtlinux-3.0/schedulers/i386/rtl_time.c Tue Oct 10 14:56:03 2000
@@ -30,10 +30,17 @@
#include <rtl_time.h>
/* #define CONFIG_RTL_FAST_8254 */
+
int notsc=0;
+int usecnt1=0;
+
+MODULE_PARM(usecnt1,"i");
MODULE_PARM(notsc,"i");
+
int _8254_latency = 0;
+
+
hrtime_t _gethrtime(struct rtl_clock *c)
{
return gethrtime();
@@ -59,6 +66,9 @@
#define READ_CNT0(var) \
do { var = inb(0x40); var |= (inb(0x40) << 8); } while (0)
+#define READ_CNT1(var) \
+do { var = inb(0x41); var |= (inb(0x41) << 8); } while (0)
+
#define READ_CNT2(var) \
do { var = inb(0x42); var |= (inb(0x42) << 8); } while (0)
@@ -69,6 +79,9 @@
#define LATCH_CNT0_AND_2() \
outb(0xda, 0x43);
+#define LATCH_CNT1() \
+outb(0xd4, 0x43);
+
#define LATCH_CNT2() \
outb(0xd8, 0x43);
@@ -91,6 +104,7 @@
static volatile int last_c2;
unsigned long scaler_8254_to_hrtime; /* =8380965 ns*100 */
unsigned long scaler_hrtime_to_8254;
+
#define LATCH2 0x8000
/*static */spinlock_t lock8254;
@@ -116,8 +130,16 @@
long t;
rtl_spin_lock_irqsave (&lock8254, flags);
- LATCH_CNT2();
- READ_CNT2(c2);
+ if(usecnt1)
+ {
+ LATCH_CNT1();
+ READ_CNT1(c2);
+ }
+ else
+ {
+ LATCH_CNT2();
+ READ_CNT2(c2);
+ }
offset_time += ((c2 < last_c2) ? (last_c2 - c2) / 2 : (last_c2 - c2 + LATCH2)
/ 2);
last_c2 = c2;
if (offset_time >= CLOCK_TICK_RATE) {
@@ -296,10 +318,18 @@
outb((inb(0x61) & ~0x02) | 0x01, 0x61);
- outb_p(0xb6, 0x43); /* binary, mode 3, LSB/MSB, ch 2 */
- outb(CLATCH & 0xff, 0x42); /* LSB of count */
- outb(CLATCH >> 8, 0x42); /* MSB of count */
-
+ if(usecnt1)
+ {
+ outb_p(0x76, 0x43); /* binary, mode 3, LSB/MSB, ch 2 */
+ outb(CLATCH & 0xff, 0x41); /* LSB of count */
+ outb(CLATCH >> 8, 0x41); /* MSB of count */
+ }
+ else
+ {
+ outb_p(0xb6, 0x43); /* binary, mode 3, LSB/MSB, ch 2 */
+ outb(CLATCH & 0xff, 0x42); /* LSB of count */
+ outb(CLATCH >> 8, 0x42); /* MSB of count */
+ }
wait_cycle();
if (do_tsc)
rdtscll(t1);
@@ -396,14 +426,30 @@
} else {
do_calibration(0);
can_change_latch2 = 0;
- /* program channel 2 of the 8254 chip for periodic counting */
- outb_p(0xb6, 0x43); /* binary, mode 3, LSB/MSB, ch 2 */
- outb_p(LATCH2 & 0xff, 0x42);
- outb_p((LATCH2 >> 8) & 0xff, 0x42);
- outb_p((inb_p(0x61) & 0xfd) | 1, 0x61); /* shut up the speaker and
enable counting */
-
- LATCH_CNT2();
- READ_CNT2(last_c2);
+ if(usecnt1)
+ {
+ /* program channel 1 of the 8254 chip for periodic counting */
+ outb_p(0x76, 0x43); /* binary, mode 3, LSB/MSB, ch 2 */
+ outb_p(LATCH2 & 0xff, 0x41);
+ outb_p((LATCH2 >> 8) & 0xff, 0x41);
+ LATCH_CNT1();
+ READ_CNT1(last_c2);
+ can_change_latch2 = 1;
+ outb_p(0xb6, 0x43);
+ outb_p(2000 & 0xff, 0x42);
+ outb_p((2000 >> 8) & 0xff, 0x42);
+
+ }
+ else
+ {
+ /* program channel 2 of the 8254 chip for periodic counting */
+ outb_p(0xb6, 0x43); /* binary, mode 3, LSB/MSB, ch 2 */
+ outb_p(LATCH2 & 0xff, 0x42);
+ outb_p((LATCH2 >> 8) & 0xff, 0x42);
+ outb_p((inb_p(0x61) & 0xfd) | 1, 0x61); /* shut up the speaker
+and enable counting */
+ LATCH_CNT2();
+ READ_CNT2(last_c2);
+ }
offset_time = 0;
base_time = 0;
rtl_do_get_time = global_8254_gettime;
-- [rtl] ---
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---
For more information on Real-Time Linux see:
http://www.rtlinux.org/rtlinux/
