RTL folks,
I'm doing a bunch of jitter and timing tests and I want to disable the Pentium
cache for some of this. Searching the rtl mail archive, I see some of you have
done this.
Paulo Mantegazza wrote:
>
If you disable the cache then things are more stable but you can be catched by
the raptus to throw the PC out of the window. Try and see what happen when Linux
boots up. That's why the first Celerons were
almost pure s.....
<
Steve Rosenbluth wrote:
>
Attached is some DOS code which disables the cache on an Intel processor
supporting these 486 instructions. My AMD586-133 machine ran terribly slow,
unable to keep up with 115200bps serial, after disabling the cache.
...
; file: discache.asm
; sets sr0 bit 30 to disablef on-chip cache
...
mov edx,cr0 ;get cr0
push edx ;save cr0 on stack so we can see it
or edx,40000000H ;set bit 30 high
push edx ;save cr0 on stack so we can see it
mov cr0,edx ; disable the cache
...
<
I also notice from the Pentium manual that you need to call WBINVD to flush the
cache and prevent already-cached data from being used again.
A little knowledge is a dangerous thing and tried massaging Steve's code into an
__asm__ function that compiled, linked into main, and then segmentation faulted
when ran as root. I strongly suspect that there needs to be a bunch of prologue
code to set up the processor to be in the right mode for the CR0 access and
privileged WBINVD to work.
Does anyone have code that does this that can be run as a user-level program,
e.g., cacheoff/cacheon?
--Fred
--
Frederick M. Proctor
Group Leader, Control Systems Group
National Institute of Standards and Technology
100 Bureau Drive, Stop 8230
Gaithersburg, MD 20899-8230
301-975-3425 (voice)
301-990-9688 (fax)
[EMAIL PROTECTED] (email)
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