hello
i try to write two rt module in order to read data coming from serial
ports
i try to use interrupts. the speed of the serial ports is 500kbaud
the com3 has irq5 and the com4 has irq 7
my code is working for com3 but i mean i have a problem of priority
between irq 5 and 7 because i never get datas arriving on com4 whereas
the code for com4 is the same.
i use rtl3.0
can you tell me if i made a mistake in my code
if you know a solution i thank you in advance
joseph.
#include <rtl_sync.h>
#include <rtl_core.h>
#include <rtl.h>
#include <asm/io.h>
#include <time.h>
#include <pthread.h>
#include <rtl_fifo.h>
#include <rtl_sched.h>
#include "def_moxa.h"
unsigned char test[6];
unsigned char donnee[732];
hrtime_t debut_com3;
int i_com3=0, j_com3=0;
unsigned int handler_com3(void)
{ WORD adresse_base_com3=COM3;
unsigned char temp;
unsigned int nouveau_debut=1;
int test_rtf;
int ro[361];
hrtime_t temps_com3, tampon_temps_com3;
double temps;
temp = inb(adresse_base_com3);
i_com3++;
// rtl_printf("\n handler com3");
if(i_com3==732)
{ i_com3=0;
tampon_temps_com3=clock_gethrtime(CLOCK_REALTIME);
temps_com3=tampon_temps_com3-debut_com3;
temps=(double)(temps_com3/1000000);
rtl_printf("\n\n avant %ld",(long int)temps);
for (i_com3=0; i_com3<=720; i_com3+=2)
{ ro[i_com3/2] = (donnee[8+i_com3])+(256*(donnee[9+i_com3]));
// rtl_printf(" %d ",ro[i_com3/2]);
}
//debut_com3 = tampon_temps_com3;
i_com3=0;
}
test[0]=test[1];
test[1]=test[2];
test[2]=test[3];
test[3]=test[4];
test[4]=test[5];
test[5]=temp;
if(test[0]==0x02 && test[1]==0x80 && test[2]== 0xD6 && test[3]==0x02
&& test[4]==0xB0 && test[5]==0x69 )
{ for(j_com3=0; j_com3<6; j_com3++)
donnee[j_com3]=test[j_com3];
i_com3=j_com3;
debut_com3=clock_gethrtime(CLOCK_REALTIME);
}
donnee[i_com3]=temp;
rtl_hard_enable_irq(5);
return 0;
}
int init_module(void)
{
int Erreur = 0;
BYTE i,tampon;
WORD adresse_base_com3=COM3;
WORD dll = adresse_base_com3 + DLL;
WORD dlm = adresse_base_com3 + DLM;
WORD ier = adresse_base_com3 + IER;
WORD lcr = adresse_base_com3 + LCR;
rtl_irqstate_t f_com3;
int test_irq=0;
/* Nettoyage du port */
for (i=0;i<=6;i++)
inb(adresse_base_com3);
outb(0x00,ier); /* disable l'IT reception */
/* Initialisation de la vitesse de communication */
outb(0x80,lcr); /* LCR.7 = 1 */
outb((B500ka & 255),dll); /* partie basse */
outb(( B500ka>> 8),dlm); /* partie haute */
/* Initialisation de la largeur du caractere, du bit de stop
et de la parite */
outb(( BIT_8 | (0 << 2) | (P_AUCUNE << 3) ),lcr );
outb(0x02,adresse_base_com3 +2); // Raz FIFO
outb(0x01,adresse_base_com3 +2); // val. FIFO mode DMA
outb(0x01,ier); /* enable l'IT reception */
inb(adresse_base_com3); /* On vide RXD */
inb(adresse_base_com3);
debut_com3=clock_gethrtime(CLOCK_REALTIME);
rtl_no_interrupts(f_com3);
rtl_request_irq(5,handler_com3);
rtl_printf("\n test test_request_irq %d",test_irq);
rtl_hard_enable_irq(5);
// rtl_printf("\n test hard_enable %d",test_irq);
rtl_restore_interrupts(f_com3);
// rtl_printf("\n test restore %d",test_irq);
return 0;
}
void cleanup_module(void)
{
rtl_free_irq(5);
}
#include <rtl_sync.h>
#include <rtl_core.h>
#include <rtl.h>
#include <asm/io.h>
#include <time.h>
#include <pthread.h>
#include <rtl_fifo.h>
#include "def_moxa.h"
unsigned char test_com4[6];
unsigned char donnee_com4[732];
int i_com4=0, j_com4=0, passage=0;
unsigned int handler_com4(void)
{ WORD adresse_base_com4=COM4;
unsigned char temp;
unsigned int nouveau_debut=1;
int test_rtf;
int ro[361];
temp = inb(adresse_base_com4);
i_com4++;
rtl_printf("\n handler com4");
if(i_com4==732)
{ i_com4=0;
rtl_printf("\n\n arriere %d",passage); passage++;
for (i_com4=0; i_com4<=720; i_com4+=2)
{ ro[i_com4/2] = (donnee_com4[8+i_com4])+(256*(donnee_com4[9+i_com4]));
// rtl_printf(" %d ",ro[i_com4/2]);
}
i_com4=0;
}
test_com4[0]=test_com4[1];
test_com4[1]=test_com4[2];
test_com4[2]=test_com4[3];
test_com4[3]=test_com4[4];
test_com4[4]=test_com4[5];
test_com4[5]=temp;
if(test_com4[0]==0x02 && test_com4[1]==0x80 && test_com4[2]== 0xD6 &&
test_com4[3]==0x02
&& test_com4[4]==0xB0 && test_com4[5]==0x69 )
{ for(j_com4=0; j_com4<6; j_com4++)
donnee_com4[j_com4]=test_com4[j_com4];
i_com4=j_com4;
//rtl_printf(" %x ",test_com4[j_com4]);
}
donnee_com4[i_com4]=temp;
rtl_hard_enable_irq(7);
return 0;
}
int init_module(void)
{
int Erreur = 0;
BYTE i,tampon;
WORD adresse_base_com4=COM4;
WORD dll = adresse_base_com4 + DLL;
WORD dlm = adresse_base_com4 + DLM;
WORD ier = adresse_base_com4 + IER;
WORD lcr = adresse_base_com4 + LCR;
rtl_irqstate_t f_com4;
int test_irq=0;
/* Nettoyage du port */
for (i=0;i<=6;i++)
inb(adresse_base_com4);
outb(0x00,ier); /* disable l'IT reception */
/* Initialisation de la vitesse de communication */
outb(0x80,lcr); /* LCR.7 = 1 */
outb((B500ka & 255),dll); /* partie basse */
outb(( B500ka>> 8),dlm); /* partie haute */
/* Initialisation de la largeur du caractere, du bit de stop
et de la parite */
outb(( BIT_8 | (0 << 2) | (P_AUCUNE << 3) ),lcr );
outb(0x02,adresse_base_com4 +2); // Raz FIFO
outb(0x01,adresse_base_com4 +2); // val. FIFO mode DMA
outb(0x01,ier); /* enable l'IT reception */
inb(adresse_base_com4); /* On vide RXD */
inb(adresse_base_com4);
rtl_no_interrupts(f_com4);
rtl_request_irq(7,handler_com4);
rtl_printf("\n test test_request_irq %d",test_irq);
rtl_hard_enable_irq(7);
// rtl_printf("\n test hard_enable %d",test_irq);
rtl_restore_interrupts(f_com4);
// rtl_printf("\n test restore %d",test_irq);
return 0;
}
void cleanup_module(void)
{
rtl_free_irq(7);
}
