Hi Mr Wright,
I'm designing a data acquisition system based on ZFx86(a 486 based SoC) and
RT-Linux. I use an FPGA to read data directly from ADCs and transfer them to main
momory(as PCI bus master).
The FPGA can only deal with physical address space easily, so I choose the
above-linux RAM for buffer. But I have some questions about this way.
1. I need a large buffer.
My system has 128MB RAM in total and I leave only 16MB for linux by writing
"append="mem=16m"" in lilo.conf and getting a virtual address point by mmap(). From my
real-time program, it seems I can read from and write to the entire buffer(128MB-16MB)
properly. But an article from Frederick M. Proctor
(http://www.isd.mel.nist.gov/projects/emc/emcsoft.html) says 'The size of the shared
memory pool must be less than the pagesize declared in /usr/include/asm/param.h. In
Intel Pentium class machine and above, the page size is 4MB. On earlier machines, the
page size is 1MB'. What will happen if my buffer size larger than 4MB or 1MB? Maybe
there will be long delay when crossing page boundary, which is dangerous to a
real-time system.
2. The buffer should be non-cacheable.
The FPGA refresh the buffer automatically, but the real-time program must
always get newest data from the buffer. So the buffer should be non-cacheable, or the
CPU will get old data if cache hit. Do you have any suggestion on this? My system
seems OK, but I'm NOT sure whether I will meet trouble in the future.
3. How to make PCI faster?
Your system can achieve 89MB/s, but mine is much slower. The FPGA is the only
PCI peripheral in my system, but by an oscilloscope, I find the PCI bursting cycles
always broken, the request-and-grant pairs cost much time. Can you give me some advice
here?
Thank you.
Best regards
Jiang Wanli
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