M. Koehrer wrote: > Hi Jan, > > one changed part that I have identified in the ISR (e100intr()) of e100 are > the function calls to > e100_disable_clear_intr() and e100_set_intr_mask() that lead to additional > accesses > to the NIC's (status, mask) registers. > And the patch was intended to do exactly the same accesses at eepro100.
And that's not bad as we now have a working reference.
>
> Also, the e100intr processes only one interrupt at a time, i.e. it does not
> have the
> do { } while(1); loop. This is the second part I modified.
That depends on the model. Intel's stand-alone driver also still
supports non-NAPI, i.e. the "classic" loop in the IRQ handler. The
kernel now only knows NAPI: ack the IRQ and schedule some polling on the
device in a bottom-half context (or task, can't tell right now).
>
> O.K. I will try to break it down.
>
Great.
Thanks,
Jan
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