Hi Jan,
I join with this email the patch, don't hesitate email me if it is not
correct. I solve my oops problem by modifying the driver_remove routine. I
think the driver is now operational, the source code seems to be OK too.
Thanks for all,
WALLOIS Cyril
diff -u -r rtnet_old/configure.ac rtnet/configure.ac
--- rtnet_old/configure.ac 2010-04-28 00:17:50.000000000 +0200
+++ rtnet/configure.ac 2010-04-12 10:22:19.804035000 +0200
@@ -1039,6 +1036,16 @@
AC_MSG_RESULT([${CONFIG_RTNET_DRV_IGB:-n}])
AM_CONDITIONAL(CONFIG_RTNET_DRV_IGB,[test "$CONFIG_RTNET_DRV_IGB" = "y"])
+AC_MSG_CHECKING([whether to build DM9000 Ethernet driver])
+AC_ARG_ENABLE(dm9000,
+ AS_HELP_STRING([--enable-dm9000], [build dm9000 Ethernet driver]),
+ [case "$enableval" in
+ y | yes) CONFIG_RTNET_DRV_DM9000=y ;;
+ *) CONFIG_RTNET_DRV_DM9000=n ;;
+ esac])
+AC_MSG_RESULT([${CONFIG_RTNET_DRV_DM9000:-n}])
+AM_CONDITIONAL(CONFIG_RTNET_DRV_DM9000,[test "$CONFIG_RTNET_DRV_DM9000" = "y"])
+
dnl ======================================================================
dnl Stack parameters
dnl ======================================================================
diff -u -r rtnet_old/drivers/GNUmakefile.am rtnet/drivers/GNUmakefile.am
--- rtnet_old/drivers/GNUmakefile.am 2010-04-28 00:17:50.000000000 +0200
+++ rtnet/drivers/GNUmakefile.am 2010-04-12 10:19:38.572035000 +0200
@@ -34,6 +34,7 @@
libkernel_pcnet32.a \
libkernel_smc91111.a \
libkernel_macb.a \
+ libkernel_dm9000.a \
libkernel_via-rhine.a
RTEXT_KMOD_CFLAGS += $(RTFW_KMOD_CFLAGS)
@@ -146,6 +147,15 @@
libkernel_via_rhine_a_SOURCES = \
rt_via-rhine.c
+libkernel_dm9000_a_CPPFLAGS = \
+ $(RTEXT_KMOD_CFLAGS) \
+ -I$(top_srcdir)/stack/include \
+ -I$(top_builddir)/stack/include
+
+libkernel_dm9000_a_SOURCES = \
+ rt_dm9000.c \
+ rt_dm9000.h
+
OBJS =
@@ -201,6 +211,10 @@
OBJS += rt_via-rhine$(modext)
endif
+if CONFIG_RTNET_DRV_DM9000
+OBJS += rt_dm9000$(modext)
+endif
+
rt_8139too.o: libkernel_8139too.a
$(LD) --whole-archive $< -r -o $@
@@ -240,6 +254,9 @@
rt_via-rhine.o: libkernel_via-rhine.a
$(LD) --whole-archive $< -r -o $@
+rt_dm9000.o: libkernel_dm9000.a
+ $(LD) --whole-archive $< -r -o $@
+
all-local: all-local$(modext)
# 2.4 build
@@ -258,6 +275,7 @@
$(libkernel_pcnet32_a_SOURCES) \
$(libkernel_smc91111_a_SOURCES) \
$(libkernel_macb_a_SOURCES) \
+ $(libkernel_dm9000_a_SOURCES) \
$(libkernel_via_rhine_a_SOURCES) FORCE
$(RTNET_KBUILD_CMD)
@@ -280,6 +298,7 @@
$(libkernel_pcnet32_a_SOURCES) \
$(libkernel_smc91111_a_SOURCES) \
$(libkernel_macb_a_SOURCES) \
+ $(libkernel_dm9000_a_SOURCES) \
$(libkernel_via_rhine_a_SOURCES)
$(RTNET_KBUILD_CLEAN)
diff -u -r rtnet_old/drivers/Kconfig rtnet/drivers/Kconfig
--- rtnet_old/drivers/Kconfig 2010-04-28 00:17:50.000000000 +0200
+++ rtnet/drivers/Kconfig 2010-04-28 11:37:08.400030633 +0200
@@ -101,6 +101,9 @@
config RTNET_DRV_AT91ETHER
bool "AT91RM9200 Board Ethernet Driver"
+config RTNET_DRV_DM9000
+ bool "Armadeus Board Ethernet Driver"
+
config RTNET_DRV_MACB
bool "MACB AT91SAM926x devices"
---help---
Seulement dans rtnet/drivers: rt_dm9000.c
Seulement dans rtnet/drivers: rt_dm9000.h
/*
* Davicom DM9000 Fast Ethernet driver for Linux.
* Copyright (C) 1997 Sten Wang
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
*
* Additional updates, Copyright:
* Ben Dooks <[email protected]>
* Sascha Hauer <[email protected]>
*/
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/crc32.h>
#include <linux/mii.h>
#include <linux/dm9000.h>
#include "rt_dm9000.h"
#include <linux/rtnetlink.h>/*add experimental*/
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <asm/delay.h>
#include <asm/irq.h>
#include <asm/io.h>
/* *** RTnet *** */
#include <rtnet_port.h>
#define RX_RING_SIZE 8
#define MAX_UNITS 8
#define DEFAULT_RX_POOL_SIZE 16
static int cards[MAX_UNITS] = { [0 ... (MAX_UNITS-1)] = 1 };
compat_module_int_param_array(cards, MAX_UNITS);
/* Board/System/Debug information/definition ---------------- */
#define DM9000_PHY 0x40 /* PHY address 0x01 */
#define CARDNAME "dm9000"
#define DRV_VERSION "0.2"
#define HEADER_LENGTH 14
/*
* Transmit timeout, default 5 seconds.
*/
static int watchdog = 5000;
module_param(watchdog, int, 0400);
MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
/* DM9000 register address locking.
*
* The DM9000 uses an address register to control where data written
* to the data register goes. This means that the address register
* must be preserved over interrupts or similar calls.
*
* During interrupt and other critical calls, a spinlock is used to
* protect the system, but the calls themselves save the address
* in the address register in case they are interrupting another
* access to the device.
*
* For general accesses a lock is provided so that calls which are
* allowed to sleep are serialised so that the address register does
* not need to be saved. This lock also serves to serialise access
* to the EEPROM and PHY access registers which are shared between
* these two devices.
*/
/* The driver supports the original DM9000E, and now the two newer
* devices, DM9000A and DM9000B.
*/
enum dm9000_type {
TYPE_DM9000E, /* original DM9000 */
TYPE_DM9000A,
TYPE_DM9000B
};
/* Structure/enum declaration ------------------------------- */
typedef struct board_info {
void __iomem *io_addr; /* Register I/O base address */
void __iomem *io_data; /* Data I/O address */
u16 irq; /* IRQ */
u16 tx_pkt_cnt;
u16 queue_pkt_len;
u16 queue_start_addr;
u16 dbug_cnt;
u8 io_mode; /* 0:word, 2:byte */
u8 phy_addr;
u8 imr_all;
unsigned int flags;
unsigned int in_suspend :1;
int debug_level;
enum dm9000_type type;
void (*inblk)(void __iomem *port, void *data, int length);
void (*outblk)(void __iomem *port, void *data, int length);
void (*dumpblk)(void __iomem *port, int length);
struct device *dev; /* parent device */
struct resource *addr_res; /* resources found */
struct resource *data_res;
struct resource *addr_req; /* resources requested */
struct resource *data_req;
struct resource *irq_res;
struct mutex addr_lock; /* phy and eeprom access lock */
struct delayed_work phy_poll;
struct rtnet_device *ndev;
struct rtskb *skb; /* holds skb until xmit interrupt completes */
int skb_length;
rtdm_lock_t lock;
struct mii_if_info mii; /* ethtool support */
u32 msg_enable;
/* RTNet */
struct net_device_stats stats;
rtdm_irq_t irq_handle;
rtdm_irq_t phy_irq_handle;
struct rtskb_queue skb_pool;
} board_info_t;
static inline board_info_t *to_dm9000_board(struct rtnet_device *dev)
{
return dev->priv;
}
/* DM9000 network board routine ---------------------------- */
static void
dm9000_reset(board_info_t * db)
{
/* RESET device */
writeb(DM9000_NCR, db->io_addr);
udelay(200);
writeb(NCR_RST, db->io_data);
udelay(200);
}
/*
* Read a byte from I/O port
*/
static u8
ior(board_info_t * db, int reg)
{
writeb(reg, db->io_addr);
return readb(db->io_data);
}
/*
* Write a byte to I/O port
*/
static void
iow(board_info_t * db, int reg, int value)
{
writeb(reg, db->io_addr);
writeb(value, db->io_data);
}
/* routines for sending block to chip */
static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count)
{
writesb(reg, data, count);
}
static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count)
{
writesw(reg, data, (count+1) >> 1);
}
static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count)
{
writesl(reg, data, (count+3) >> 2);
}
/* input block from chip to memory */
static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count)
{
readsb(reg, data, count);
}
static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count)
{
readsw(reg, data, (count+1) >> 1);
}
static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count)
{
readsl(reg, data, (count+3) >> 2);
}
/* dump block from chip to null */
static void dm9000_dumpblk_8bit(void __iomem *reg, int count)
{
int i;
int tmp;
for (i = 0; i < count; i++)
tmp = readb(reg);
}
static void dm9000_dumpblk_16bit(void __iomem *reg, int count)
{
int i;
int tmp;
count = (count + 1) >> 1;
for (i = 0; i < count; i++)
tmp = readw(reg);
}
static void dm9000_dumpblk_32bit(void __iomem *reg, int count)
{
int i;
int tmp;
count = (count + 3) >> 2;
for (i = 0; i < count; i++)
tmp = readl(reg);
}
/* dm9000_set_io
*
* select the specified set of io routines to use with the
* device
*/
static void dm9000_set_io(struct board_info *db, int byte_width)
{
/* use the size of the data resource to work out what IO
* routines we want to use
*/
switch (byte_width) {
case 1:
db->dumpblk = dm9000_dumpblk_8bit;
db->outblk = dm9000_outblk_8bit;
db->inblk = dm9000_inblk_8bit;
break;
case 3:
dev_dbg(db->dev, "3 byte IO, falling back to 16bit\n");
case 2:
db->dumpblk = dm9000_dumpblk_16bit;
db->outblk = dm9000_outblk_16bit;
db->inblk = dm9000_inblk_16bit;
break;
case 4:
default:
db->dumpblk = dm9000_dumpblk_32bit;
db->outblk = dm9000_outblk_32bit;
db->inblk = dm9000_inblk_32bit;
break;
}
}
static unsigned int
dm9000_read_locked(board_info_t *db, int reg)
{
unsigned int ret;
rtdm_lockctx_t context;/*rtnet experimental*/
rtdm_lock_get_irqsave(&db->lock, context);/*rtnet experimental*/
ret = ior(db, reg);
rtdm_lock_put_irqrestore(&db->lock, context); /*rtnet experimental*/
return ret;
}
static int dm9000_wait_eeprom(board_info_t *db)
{
unsigned int status;
int timeout = 8; /* wait max 8msec */
/* The DM9000 data sheets say we should be able to
* poll the ERRE bit in EPCR to wait for the EEPROM
* operation. From testing several chips, this bit
* does not seem to work.
*
* We attempt to use the bit, but fall back to the
* timeout (which is why we do not return an error
* on expiry) to say that the EEPROM operation has
* completed.
*/
while (1) {
status = dm9000_read_locked(db, DM9000_EPCR);
if ((status & EPCR_ERRE) == 0)
break;
msleep(1);
if (timeout-- < 0) {
break;
}
}
return 0;
}
/*
* Read a word data from EEPROM
*/
static void
dm9000_read_eeprom(board_info_t *db, int offset, u8 *to)
{
rtdm_lockctx_t context;/*rtnet experimental*/
if (db->flags & DM9000_PLATF_NO_EEPROM) {
to[0] = 0xff;
to[1] = 0xff;
return;
}
mutex_lock(&db->addr_lock);
rtdm_lock_get_irqsave(&db->lock, context);/*rtnet experimental*/
iow(db, DM9000_EPAR, offset);
iow(db, DM9000_EPCR, EPCR_ERPRR);
rtdm_lock_put_irqrestore(&db->lock, context); /*rtnet experimental*/
dm9000_wait_eeprom(db);
/* delay for at-least 150uS */
msleep(1);
rtdm_lock_get_irqsave(&db->lock, context);/*rtnet experimental*/
iow(db, DM9000_EPCR, 0x0);
to[0] = ior(db, DM9000_EPDRL);
to[1] = ior(db, DM9000_EPDRH);
rtdm_lock_put_irqrestore(&db->lock, context); /*rtnet experimental*/
mutex_unlock(&db->addr_lock);
}
/* dm9000_release_board
*
* release a board, and any mapped resources
*/
static void
dm9000_release_board(struct platform_device *pdev, struct board_info *db)
{
/* unmap our resources */
iounmap(db->io_addr);
iounmap(db->io_data);
/* release the resources */
rtskb_pool_release(&db->skb_pool);
release_resource(db->data_req);
kfree(db->data_req);
release_resource(db->addr_req);
kfree(db->addr_req);
}
static unsigned char dm9000_type_to_char(enum dm9000_type type)
{
switch (type) {
case TYPE_DM9000E: return 'e';
case TYPE_DM9000A: return 'a';
case TYPE_DM9000B: return 'b';
}
return '?';
}
/*
* Set DM9000 multicast address
*/
static void
dm9000_hash_table(struct rtnet_device *dev)
{
board_info_t *db = dev->priv;
struct dev_mc_list *mcptr = dev->mc_list;
int mc_cnt = dev->mc_count;
int i, oft;
u32 hash_val;
u16 hash_table[4];
u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN;
rtdm_irq_disable(&db->irq_handle);
rtdm_lock_get(&db->lock);
for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
iow(db, oft, dev->dev_addr[i]);
/* Clear Hash Table */
for (i = 0; i < 4; i++)
hash_table[i] = 0x0;
/* broadcast address */
hash_table[3] = 0x8000;
if (dev->flags & IFF_PROMISC)
rcr |= RCR_PRMSC;
if (dev->flags & IFF_ALLMULTI)
rcr |= RCR_ALL;
/* the multicast address in Hash Table : 64 bits */
for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
hash_val = ether_crc_le(6, mcptr->dmi_addr) & 0x3f;
hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
}
/* Write the hash table to MAC MD table */
for (i = 0, oft = DM9000_MAR; i < 4; i++) {
iow(db, oft++, hash_table[i]);
iow(db, oft++, hash_table[i] >> 8);
}
iow(db, DM9000_RCR, rcr);
rtdm_lock_put(&db->lock);
rtdm_irq_enable(&db->irq_handle);
}
/*
* Initialize dm9000 board ->rtnet
*/
static void
dm9000_init_dm9000(struct rtnet_device *dev)
{
board_info_t *db = dev->priv;
unsigned int imr;
/* I/O mode */
db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */
/* GPIO0 on pre-activate PHY */
iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
iow(db, DM9000_GPR, 0); /* Enable PHY */
if (db->flags & DM9000_PLATF_EXT_PHY)
iow(db, DM9000_NCR, NCR_EXT_PHY);
/* Program operating register */
iow(db, DM9000_TCR, 0); /* TX Polling clear */
iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
iow(db, DM9000_FCR, 0xff); /* Flow Control */
iow(db, DM9000_SMCR, 0); /* Special Mode */
/* clear TX status */
iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */
/* Set address filter table */
dm9000_hash_table(dev);
imr = IMR_PAR | IMR_PTM | IMR_PRM;
if (db->type != TYPE_DM9000E)
imr |= IMR_LNKCHNG;
db->imr_all = imr;
/* Enable TX/RX interrupt mask */
iow(db, DM9000_IMR, imr);
/* Init Driver variable */
db->tx_pkt_cnt = 0;
db->queue_pkt_len = 0;
}
/*
* Hardware start transmission.
* Send a packet to media from the upper layer.
*/
static int
dm9000_start_xmit(struct rtskb *skb, struct rtnet_device *dev)
{
board_info_t *db = dev->priv;
rtdm_lockctx_t context;/*experimental*/
db->skb = skb;
db->skb_length = skb->len;
db->stats.tx_bytes += skb->len;
if (db->tx_pkt_cnt > 1){
return 1;
}
rtdm_lock_irqsave(context);
/* get and patch time stamp just before the transmission */
if (skb->xmit_stamp)
*skb->xmit_stamp = cpu_to_be64(rtdm_clock_read() + *skb->xmit_stamp);
/* Move data to DM9000 TX RAM */
writeb(DM9000_MWCMD, db->io_addr);
(db->outblk)(db->io_data, skb->data,skb->len);
db->stats.tx_bytes += skb->len;
db->tx_pkt_cnt++;
/* TX control: First packet immediately send, second packet queue */
if (db->tx_pkt_cnt == 1) {
/* Set TX length to DM9000 */
iow(db, DM9000_TXPLL, skb->len);
iow(db, DM9000_TXPLH, skb->len >> 8);
/* Issue TX polling command */
iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
} else {
/* Second packet */
db->queue_pkt_len = skb->len;
rtnetif_stop_queue(dev);
}
rtdm_lock_irqrestore(context);
/* free this SKB */
dev_kfree_rtskb(skb);
return 0;
}
/*
* DM9000 interrupt handler
* receive the packet to upper layer, free the transmitted packet
*/
static void dm9000_tx_done(struct rtnet_device *dev, board_info_t *db)
{
int tx_status = ior(db, DM9000_NSR); /* Got TX status */
if (tx_status & (NSR_TX2END | NSR_TX1END)) {
/* One packet sent complete */
db->tx_pkt_cnt--;
db->stats.tx_packets++;
if (netif_msg_tx_done(db)) {
dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status);
}
/* Queue packet check & send */
if (db->tx_pkt_cnt > 0) {
iow(db, DM9000_TXPLL, db->queue_pkt_len);
iow(db, DM9000_TXPLH, db->queue_pkt_len >> 8);
iow(db, DM9000_TCR, TCR_TXREQ);
}
rtnetif_wake_queue(dev);
}
}
struct dm9000_rxhdr {
u8 RxPktReady;
u8 RxStatus;
__le16 RxLen;
} __attribute__((__packed__));
/*
* Received a packet and pass to upper layer
*/
static void
dm9000_rx(struct rtnet_device *dev,nanosecs_abs_t *time_stamp)
{
board_info_t *db = dev->priv;
struct dm9000_rxhdr rxhdr;
struct rtskb *skb;
u8 rxbyte, *rdptr;
bool GoodPacket;
int RxLen;
/* Check packet ready or not */
do {
ior(db, DM9000_MRCMDX); /* Dummy read */
/* Get most updated data */
rxbyte = readb(db->io_data);
/* Status check: this byte must be 0 or 1 */
if (rxbyte > DM9000_PKT_RDY) {
iow(db, DM9000_RCR, 0x00); /* Stop Device */
iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */
return;
}
if (rxbyte != DM9000_PKT_RDY){
return;
}
/* A packet ready now & Get status/length */
GoodPacket = true;
writeb(DM9000_MRCMD, db->io_addr);
(db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr));
RxLen = le16_to_cpu(rxhdr.RxLen);
if (netif_msg_rx_status(db))
dev_dbg(db->dev, "RX: status %02x, length %04x\n",
rxhdr.RxStatus, RxLen);
/* Packet Status check */
if (RxLen < 0x40) {
GoodPacket = false;
if (netif_msg_rx_err(db))
dev_dbg(db->dev, "RX: Bad Packet (runt)\n");
}
if (RxLen > DM9000_PKT_MAX) {
dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen);
}
/* rxhdr.RxStatus is identical to RSR register. */
if (rxhdr.RxStatus & (RSR_FOE | RSR_CE | RSR_AE |
RSR_PLE | RSR_RWTO |
RSR_LCS | RSR_RF)) {
GoodPacket = false;
if (rxhdr.RxStatus & RSR_FOE) {
if (netif_msg_rx_err(db))
dev_dbg(db->dev, "fifo error\n");
db->stats.rx_fifo_errors++;
}
if (rxhdr.RxStatus & RSR_CE) {
if (netif_msg_rx_err(db))
dev_dbg(db->dev, "crc error\n");
db->stats.rx_crc_errors++;
}
if (rxhdr.RxStatus & RSR_RF) {
if (netif_msg_rx_err(db))
dev_dbg(db->dev, "length error\n");
db->stats.rx_length_errors++;
}
}
/* Move data from DM9000 */
if (GoodPacket
&& ((skb = dev_alloc_rtskb(RxLen + 4, &db->skb_pool)) != NULL)) {
rtskb_reserve(skb, 2);
rdptr = (u8 *) rtskb_put(skb, RxLen - 4);
skb->rtdev = db->ndev;
skb->time_stamp = *time_stamp;
/* Read received packet from RX SRAM */
(db->inblk)(db->io_data, rdptr, RxLen);
db->stats.rx_bytes += RxLen;
/* Pass to upper layer */
skb->protocol = rt_eth_type_trans(skb, dev);
rtnetif_rx(skb);
db->stats.rx_packets++;
} else {
/* need to dump the packet's data */
(db->dumpblk)(db->io_data, RxLen);
}
} while (rxbyte == DM9000_PKT_RDY);
}
static int dm9000_interrupt(rtdm_irq_t *irq_handle)
{
nanosecs_abs_t time_stamp = rtdm_clock_read();
struct rtnet_device *dev = rtdm_irq_get_arg(irq_handle, struct rtnet_device);
board_info_t *db = dev->priv;
int int_status;
unsigned int old_packet_cnt = db->stats.rx_packets;
u8 reg_save;
/* A real interrupt coming */
/* holders of db->lock must always block IRQs */
rtdm_lock_get(&db->lock);
/* Save previous register address */
reg_save = readb(db->io_addr);
/* Disable all interrupts */
iow(db, DM9000_IMR, IMR_PAR);
/* Got DM9000 interrupt status */
int_status = ior(db, DM9000_ISR); /* Got ISR */
iow(db, DM9000_ISR, int_status); /* Clear ISR status */
if (netif_msg_intr(db))
dev_dbg(db->dev, "interrupt status %02x\n", int_status);
/* Received the coming packet */
if (int_status & ISR_PRS){
dm9000_rx(dev,&time_stamp);
}
/* Transmit Interrupt check */
if (int_status & ISR_PTS){
dm9000_tx_done(dev, db);
}
/* Re-enable interrupt mask */
iow(db, DM9000_IMR, db->imr_all);
/* Restore previous register address */
writeb(reg_save, db->io_addr);
rtdm_lock_put(&db->lock);
if (old_packet_cnt != db->stats.rx_packets)
rt_mark_stack_mgr(dev);
return RTDM_IRQ_HANDLED;
}
#ifdef CONFIG_NET_POLL_CONTROLLER
/*
*Used by netconsole
*/
static void dm9000_poll_controller(struct rtnet_device *dev)
{
disable_irq(dev->irq);
dm9000_interrupt(dev->irq, dev);
enable_irq(dev->irq);
}
#endif
/*
* Open the interface.
* The interface is opened whenever "ifconfig" actives it.
*/
static int
dm9000_open(struct rtnet_device *dev)
{
board_info_t *db = dev->priv;
unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK;
int retval;
if (netif_msg_ifup(db))
dev_dbg(db->dev, "enabling %s\n", dev->name);
/* If there is no IRQ type specified, default to something that
* may work, and tell the user that this is a problem */
if (irqflags == IRQF_TRIGGER_NONE)
dev_dbg(db->dev, "WARNING: no IRQ resource flags set.\n");
irqflags |= IRQF_SHARED;
/* Initialize DM9000 board */
dm9000_reset(db);
dm9000_init_dm9000(dev);
rt_stack_connect(dev, &STACK_manager);
retval = rtdm_irq_request(&db->irq_handle,dev->irq, dm9000_interrupt,0, dev->name, dev);
if (retval)
return -EAGAIN;
/* Init driver variable */
db->dbug_cnt = 0;
rtnetif_start_queue(dev);
return 0;
}
/*
* Sleep, either by using msleep() or if we are suspending, then
* use mdelay() to sleep.
*/
static void dm9000_msleep(board_info_t *db, unsigned int ms)
{
if (db->in_suspend)
mdelay(ms);
else
msleep(ms);
}
/*
* Write a word to phyxcer
*/
static void
dm9000_phy_write(struct rtnet_device *dev,
int phyaddr_unused, int reg, int value)
{
board_info_t *db = dev->priv;
unsigned long reg_save;
rtdm_lockctx_t context;/*rtnet experimental*/
mutex_lock(&db->addr_lock);
rtdm_lock_get_irqsave(&db->lock, context);/*rtnet experimental*/
/* Save previous register address */
reg_save = readb(db->io_addr);
/* Fill the phyxcer register into REG_0C */
iow(db, DM9000_EPAR, DM9000_PHY | reg);
/* Fill the written data into REG_0D & REG_0E */
iow(db, DM9000_EPDRL, value);
iow(db, DM9000_EPDRH, value >> 8);
iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW); /* Issue phyxcer write command */
writeb(reg_save, db->io_addr);
rtdm_lock_put_irqrestore(&db->lock, context); /*rtnet experimental*/
dm9000_msleep(db, 1); /* Wait write complete */
rtdm_lock_get_irqsave(&db->lock, context);/*rtnet experimental*/
reg_save = readb(db->io_addr);
iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
/* restore the previous address */
writeb(reg_save, db->io_addr);
rtdm_lock_put_irqrestore(&db->lock, context); /*rtnet experimental*/
mutex_unlock(&db->addr_lock);
}
static void
dm9000_shutdown(struct rtnet_device *dev)
{
board_info_t *db = dev->priv;
/* RESET device */
dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */
iow(db, DM9000_RCR, 0x00); /* Disable RX */
}
/*
* Stop the interface.
* The interface is stopped when it is brought.
*/
static int
dm9000_stop(struct rtnet_device *ndev)
{
board_info_t *db = ndev->priv;// netdev_priv(ndev);
if (netif_msg_ifdown(db))
dev_dbg(db->dev, "shutting down %s\n", ndev->name);
rtnetif_stop_queue(ndev);
rtnetif_carrier_off(ndev);
dm9000_shutdown(ndev);
/* free interrupt */
rtdm_irq_free(&db->irq_handle);
rt_stack_disconnect(ndev);
return 0;
}
#define res_size(_r) (((_r)->end - (_r)->start) + 1)
/*
* Search DM9000 board, allocate space and register it
*/
static int __devinit
dm9000_probe(struct platform_device *pdev)
{
struct dm9000_plat_data *pdata = pdev->dev.platform_data;
struct board_info *db; /* Point a board information structure */
struct rtnet_device *ndev;
const unsigned char *mac_src;
int ret = 0;
int iosize;
int i;
u32 id_val;
static int cards_found = -1;
cards_found++;
if (cards[cards_found] == 0)
return -ENODEV;
/* Init network device */
ndev = rt_alloc_etherdev(sizeof(struct board_info));/*rtnet*/
if (!ndev) {
return -ENOMEM;
}
rtdev_alloc_name(ndev, "rteth%d");
rt_rtdev_connect(ndev, &RTDEV_manager);
RTNET_SET_MODULE_OWNER(ndev);
ndev->vers = RTDEV_VERS_2_0;
/* setup board info structure */
db = ndev->priv;
memset(db, 0, sizeof(*db));
db->dev = &pdev->dev;
db->ndev = ndev;
rtdm_lock_init(&db->lock);
mutex_init(&db->addr_lock);
db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (db->addr_res == NULL || db->data_res == NULL ||
db->irq_res == NULL) {
dev_dbg(db->dev, "insufficient resources\n");
ret = -ENOENT;
goto out;
}
iosize = res_size(db->addr_res);
db->addr_req = request_mem_region(db->addr_res->start, iosize,
pdev->name);
if (db->addr_req == NULL) {
dev_dbg(db->dev, "cannot claim address reg area\n");
ret = -EIO;
goto out;
}
db->io_addr = ioremap(db->addr_res->start, iosize);
if (db->io_addr == NULL) {
dev_dbg(db->dev, "failed to ioremap address reg\n");
ret = -EINVAL;
goto out;
}
iosize = res_size(db->data_res);
db->data_req = request_mem_region(db->data_res->start, iosize,
pdev->name);
if (db->data_req == NULL) {
dev_dbg(db->dev, "cannot claim data reg area\n");
ret = -EIO;
goto out;
}
db->io_data = ioremap(db->data_res->start, iosize);
if (db->io_data == NULL) {
dev_dbg(db->dev, "failed to ioremap data reg\n");
ret = -EINVAL;
goto out;
}
/* Get I/O base address and IRQ */
ndev->base_addr = (unsigned long)db->io_addr;
ndev->irq = platform_get_irq(pdev, 0);//db->irq_res->start;
/* ensure at least we have a default set of IO routines */
dm9000_set_io(db, iosize);
/* check to see if anything is being over-ridden */
if (pdata != NULL) {
/* check to see if the driver wants to over-ride the
* default IO width */
if (pdata->flags & DM9000_PLATF_8BITONLY)
dm9000_set_io(db, 1);
if (pdata->flags & DM9000_PLATF_16BITONLY)
dm9000_set_io(db, 2);
if (pdata->flags & DM9000_PLATF_32BITONLY)
dm9000_set_io(db, 4);
/* check to see if there are any IO routine
* over-rides */
if (pdata->inblk != NULL)
db->inblk = pdata->inblk;
if (pdata->outblk != NULL)
db->outblk = pdata->outblk;
if (pdata->dumpblk != NULL)
db->dumpblk = pdata->dumpblk;
db->flags = pdata->flags;
}
#ifdef CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL
db->flags |= DM9000_PLATF_SIMPLE_PHY;
#endif
dm9000_reset(db);
/* try multiple times, DM9000 sometimes gets the read wrong */
for (i = 0; i < 8; i++) {
id_val = ior(db, DM9000_VIDL);
id_val |= (u32)ior(db, DM9000_VIDH) << 8;
id_val |= (u32)ior(db, DM9000_PIDL) << 16;
id_val |= (u32)ior(db, DM9000_PIDH) << 24;
if (id_val == DM9000_ID)
break;
dev_dbg(db->dev, "read wrong id 0x%08x\n", id_val);
}
if (id_val != DM9000_ID) {
dev_dbg(db->dev, "wrong id: 0x%08x\n", id_val);
ret = -ENODEV;
goto out;
}
/* Identify what type of DM9000 we are working on */
id_val = ior(db, DM9000_CHIPR);
dev_dbg(db->dev, "dm9000 revision 0x%02x\n", id_val);
switch (id_val) {
case CHIPR_DM9000A:
db->type = TYPE_DM9000A;
break;
case CHIPR_DM9000B:
db->type = TYPE_DM9000B;
break;
default:
dev_dbg(db->dev, "ID %02x => defaulting to DM9000E\n", id_val);
db->type = TYPE_DM9000E;
}
/* from this point we assume that we have found a DM9000 */
/* driver system function */
ndev->open = &dm9000_open;
ndev->hard_start_xmit = &dm9000_start_xmit;
ndev->stop = &dm9000_stop;
ndev->mtu = DM9000_PKT_MAX;
#ifdef CONFIG_NET_POLL_CONTROLLER
ndev->poll_controller = &dm9000_poll_controller;
#endif
db->mii.phy_id_mask = 0x1f;
db->mii.reg_num_mask = 0x1f;
db->mii.force_media = 0;
db->mii.full_duplex = 0;
mac_src = "eeprom";
if (rtskb_pool_init(&db->skb_pool, RX_RING_SIZE*2) < RX_RING_SIZE*2)
{
rtskb_pool_release(&db->skb_pool);
rtdev_free(ndev->priv);
ndev->priv = NULL;
return -ENOMEM;
}
/* try reading the node address from the attached EEPROM */
for (i = 0; i < 6; i += 2)
dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i);
if (!is_valid_ether_addr(ndev->dev_addr) && pdata != NULL) {
mac_src = "platform data";
memcpy(ndev->dev_addr, pdata->dev_addr, 6);
}
if (!is_valid_ether_addr(ndev->dev_addr)) {
/* try reading from mac */
mac_src = "chip";
for (i = 0; i < 6; i++)
ndev->dev_addr[i] = ior(db, i+DM9000_PAR);
}
if (!is_valid_ether_addr(ndev->dev_addr))
dev_dbg(db->dev, "%s: Invalid ethernet MAC address. Please "
"set using ifconfig\n", ndev->name);
platform_set_drvdata(pdev, ndev);
ret = rt_register_rtnetdev(ndev);
if (ret == 0)
rtdm_printk("%s: dm9000%c at %p,%p IRQ %d MAC: %pM (%s)\n",
ndev->name, dm9000_type_to_char(db->type),
db->io_addr, db->io_data, ndev->irq,
ndev->dev_addr, mac_src);
return 0;
out:
dev_dbg(db->dev, "not found (%d).\n", ret);
dm9000_release_board(pdev, db);
rtdev_free(ndev);
return ret;
}
static int __devexit
dm9000_drv_remove(struct platform_device *pdev)
{
struct rtnet_device *ndev = platform_get_drvdata(pdev);
board_info_t *db = (board_info_t *) ndev->priv;
rt_unregister_rtnetdev(ndev);
rt_rtdev_disconnect(ndev);
/* unmap our resources */
iounmap(db->io_addr);
iounmap(db->io_data);
/* release the resources */
rtskb_pool_release(&db->skb_pool);
release_resource(db->data_req);
kfree(db->data_req);
release_resource(db->addr_req);
kfree(db->addr_req);
platform_set_drvdata(pdev, NULL);
rtdev_free(ndev); /* free device structure */
ndev->priv = NULL;
dev_dbg(&pdev->dev, "released and freed device\n");
return 0;
}
static struct platform_driver dm9000_driver = {
.driver = {
.name = "dm9000",
.owner = THIS_MODULE,
},
.probe = dm9000_probe,
.remove = __devexit_p(dm9000_drv_remove),
};
static int __init
dm9000_init(void)
{
printk(KERN_INFO "%s Real Time Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION);
return platform_driver_register(&dm9000_driver);
}
static void __exit
dm9000_cleanup(void)
{
platform_driver_unregister(&dm9000_driver);
}
module_init(dm9000_init);
module_exit(dm9000_cleanup);
MODULE_AUTHOR("WALLOIS Cyril, CNRS");
MODULE_DESCRIPTION("Davicom DM9000 real-time network driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:dm9000");
/*
* dm9000 Ethernet
*/
#ifndef _DM9000X_H_
#define _DM9000X_H_
#define DM9000_ID 0x90000A46
/* although the registers are 16 bit, they are 32-bit aligned.
*/
#define DM9000_NCR 0x00
#define DM9000_NSR 0x01
#define DM9000_TCR 0x02
#define DM9000_TSR1 0x03
#define DM9000_TSR2 0x04
#define DM9000_RCR 0x05
#define DM9000_RSR 0x06
#define DM9000_ROCR 0x07
#define DM9000_BPTR 0x08
#define DM9000_FCTR 0x09
#define DM9000_FCR 0x0A
#define DM9000_EPCR 0x0B
#define DM9000_EPAR 0x0C
#define DM9000_EPDRL 0x0D
#define DM9000_EPDRH 0x0E
#define DM9000_WCR 0x0F
#define DM9000_PAR 0x10
#define DM9000_MAR 0x16
#define DM9000_GPCR 0x1e
#define DM9000_GPR 0x1f
#define DM9000_TRPAL 0x22
#define DM9000_TRPAH 0x23
#define DM9000_RWPAL 0x24
#define DM9000_RWPAH 0x25
#define DM9000_VIDL 0x28
#define DM9000_VIDH 0x29
#define DM9000_PIDL 0x2A
#define DM9000_PIDH 0x2B
#define DM9000_CHIPR 0x2C
#define DM9000_SMCR 0x2F
#define CHIPR_DM9000A 0x19
#define CHIPR_DM9000B 0x1B
#define DM9000_MRCMDX 0xF0
#define DM9000_MRCMD 0xF2
#define DM9000_MRRL 0xF4
#define DM9000_MRRH 0xF5
#define DM9000_MWCMDX 0xF6
#define DM9000_MWCMD 0xF8
#define DM9000_MWRL 0xFA
#define DM9000_MWRH 0xFB
#define DM9000_TXPLL 0xFC
#define DM9000_TXPLH 0xFD
#define DM9000_ISR 0xFE
#define DM9000_IMR 0xFF
#define NCR_EXT_PHY (1<<7)
#define NCR_WAKEEN (1<<6)
#define NCR_FCOL (1<<4)
#define NCR_FDX (1<<3)
#define NCR_LBK (3<<1)
#define NCR_RST (1<<0)
#define NSR_SPEED (1<<7)
#define NSR_LINKST (1<<6)
#define NSR_WAKEST (1<<5)
#define NSR_TX2END (1<<3)
#define NSR_TX1END (1<<2)
#define NSR_RXOV (1<<1)
#define TCR_TJDIS (1<<6)
#define TCR_EXCECM (1<<5)
#define TCR_PAD_DIS2 (1<<4)
#define TCR_CRC_DIS2 (1<<3)
#define TCR_PAD_DIS1 (1<<2)
#define TCR_CRC_DIS1 (1<<1)
#define TCR_TXREQ (1<<0)
#define TSR_TJTO (1<<7)
#define TSR_LC (1<<6)
#define TSR_NC (1<<5)
#define TSR_LCOL (1<<4)
#define TSR_COL (1<<3)
#define TSR_EC (1<<2)
#define RCR_WTDIS (1<<6)
#define RCR_DIS_LONG (1<<5)
#define RCR_DIS_CRC (1<<4)
#define RCR_ALL (1<<3)
#define RCR_RUNT (1<<2)
#define RCR_PRMSC (1<<1)
#define RCR_RXEN (1<<0)
#define RSR_RF (1<<7)
#define RSR_MF (1<<6)
#define RSR_LCS (1<<5)
#define RSR_RWTO (1<<4)
#define RSR_PLE (1<<3)
#define RSR_AE (1<<2)
#define RSR_CE (1<<1)
#define RSR_FOE (1<<0)
#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
#define FCTR_LWOT(ot) ( ot & 0xf )
#define IMR_PAR (1<<7)
#define IMR_ROOM (1<<3)
#define IMR_ROM (1<<2)
#define IMR_PTM (1<<1)
#define IMR_PRM (1<<0)
#define ISR_ROOS (1<<3)
#define ISR_ROS (1<<2)
#define ISR_PTS (1<<1)
#define ISR_PRS (1<<0)
#define ISR_CLR_STATUS (ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS)
#define EPCR_REEP (1<<5)
#define EPCR_WEP (1<<4)
#define EPCR_EPOS (1<<3)
#define EPCR_ERPRR (1<<2)
#define EPCR_ERPRW (1<<1)
#define EPCR_ERRE (1<<0)
#define GPCR_GEP_CNTL (1<<0)
#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
#define DM9000_PKT_MAX 1536 /* Received packet max size */
/* DM9000A / DM9000B definitions */
#define IMR_LNKCHNG (1<<5)
#define IMR_UNDERRUN (1<<4)
#define ISR_LNKCHNG (1<<5)
#define ISR_UNDERRUN (1<<4)
#endif /* _DM9000X_H_ */
------------------------------------------------------------------------------
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