BY: Suraj Kurapati (snk)
DATE: 2007-08-02 05:20
SUBJECT: RE: Having trouble dumping a vcd file
Calvin Wong wrote:
> Now as the message title says, I have difficulty generating a vcd
> file using the $dumpvars call. I edited the counter.v file and
> added 'initial $dumpvars' routine to it.
Alright.
> I also modify the advance_time method in the vpi.rb file to get
> the current time (using vpi_get_time routine) and then add the
> aNumSteps to it to produce a monotonically increasing time steps.
>
This is not necessary because the cbReadWriteSynch callback is
relative to the current simulation time.
Only the cbAtStartOfSimTime callback requires an absolute simulation
time to be specified.
> After the simulation is performed, I am left with a verilog.dump
> file but only up to 1 time tick was logged.
>
> I suspect that once the ruby execution is done, both the ruby
> simulation and the verilog (using vcs) simulation is terminated.
> When this happened , vcs does not have the time to flush out it's
> vcd logging buffer.
Yes, that seems reasonable. Good catch!
> So ... my question is if there is a way to relay control over to
> verilog so that the simulator can flush out the vcd buffer prior
> to ending the simulation?
Yes. Add the following line at the top of the
lib/ruby-vpi/runner_boot_loader.rb file:
at_exit {relay_verilog_proxy}
I will include this fix in the next release. Thanks for reporting
this bug.
