Calvin Wong wrote:
> Also, this seg faults happens only for GPL Cver and NC-Verilog.
I get the segfault with GPL Cver but not with NC-Verilog (see the
attached ncsim.log file). I have NC-Verilog version 05.83-s003.
> On vcs it works fine.
I ran it with VCS version Y-2006.06_Full64 and it didn't produce any
relevant output (see attached vcs.log file). Could you post the
output you see when you run the example in your environment?
$ rake -f cadd_tb_runner.rake vcs
(in /tmp/calvin)
vcs -R +v2k +vpi +cli -P /tmp/ruby-vpi/lib/ruby-vpi/pli.tab -load /tmp/ruby-vpi/obj/vcs.so:vlog_startup_routines_bootstrap -full64 cadd_tb.v
Warning: VCS is not officially supported on this version of Linux
assuming linux compatibility by default.
set VCS_ARCH_OVERRIDE to redhat72 or suse32 to override.
Chronologic VCS (TM)
Version Y-2006.06_Full64 -- Thu Aug 16 19:43:42 2007
Copyright (c) 1991-2006 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
***** Warning: ACC/CLI capabilities have been enabled for the entire design.
For faster performance enable module specific capability in pli.tab file
Parsing design file 'cadd_tb.v'
Top Level Modules:
cadd_tb
No TimeScale specified
Starting vcs inline pass...
1 module and 0 UDP read.
recompiling module cadd_tb
if [ -x ../simv ]; then chmod -x ../simv; fi
g++ -o ../simv 5NrI_d.o 5NrIB_d.o 30qp_1_d.o SIM_l.o /mada/software/synopsys/vcs/amd64/lib/libvirsim64.a /mada/software/synopsys/vcs/amd64/lib/libvcsnew.so -ldl -lm -lc -ldl
/usr/bin/ld: warning: libstdc++.so.5, needed by /mada/software/synopsys/vcs/amd64/lib/libvcsnew.so, may conflict with libstdc++.so.6
../simv up to date
Chronologic VCS simulator copyright 1991-2005
Contains Synopsys proprietary information.
Compiler version Y-2006.06_Full64; Runtime version Y-2006.06_Full64; Aug 16 19:44 2007
$finish at simulation time 19995
V C S S i m u l a t i o n R e p o r t
Time: 19995
CPU Time: 0.130 seconds; Data structure size: 0.0Mb
Thu Aug 16 19:44:03 2007
CPU time: .061 seconds to compile + .193 seconds to link + .177 seconds in simulation
$ rake -f cadd_tb_runner.rake ncsim
(in /tmp/calvin)
ncverilog +access+rwc +plinowarn +loadvpi=/tmp/ruby-vpi/obj/ncsim.so:vlog_startup_routines_bootstrap +nc64bit cadd_tb.v
ncverilog(64): 05.83-s003: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
file: cadd_tb.v
module worklib.cadd_tb:v
errors: 0, warnings: 0
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.cadd_tb:v <0x7d02ad80>
streams: 5, words: 1907
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 1 1
Registers: 2 2
Initial blocks: 5 5
Writing initial simulation snapshot: worklib.cadd_tb:v
Loading snapshot worklib.cadd_tb:v .................... Done
ncsim> source /mada/software/cadence/IUS583P3/tools/inca/files/ncsimrc
ncsim> run
Line 237 : T1.clk0 = 1 : Simulation time is 5
Line 230 : T0.clk0 = 1 : Simulation time is 5
Line 244 : T2.clk1 = 1 : Simulation time is 7
Line 237 : T1.clk0 = 0 : Simulation time is 10
Line 230 : T0.clk0 = 0 : Simulation time is 10
Line 251 : T3.clk1 = 0 : Simulation time is 14
Line 237 : T1.clk0 = 1 : Simulation time is 15
Line 230 : T0.clk0 = 1 : Simulation time is 15
Line 258 : Simulation time is 16
Line 237 : T1.clk0 = 0 : Simulation time is 20
Line 230 : T0.clk0 = 0 : Simulation time is 20
Line 244 : T2.clk1 = 1 : Simulation time is 21
Line 237 : T1.clk0 = 1 : Simulation time is 25
Line 230 : T0.clk0 = 1 : Simulation time is 25
Line 258 : Simulation time is 27
Line 251 : T3.clk1 = 0 : Simulation time is 28
Line 244 : T2.clk1 = 1 : Simulation time is 35
Line 258 : Simulation time is 38
Line 251 : T3.clk1 = 0 : Simulation time is 42
Line 258 : Simulation time is 49
Line 244 : T2.clk1 = 1 : Simulation time is 49
Line 251 : T3.clk1 = 0 : Simulation time is 56
Line 258 : Simulation time is 60
Line 244 : T2.clk1 = 1 : Simulation time is 63
Line 251 : T3.clk1 = 0 : Simulation time is 70
Line 278 : Simulation time is 80
scheduler.thread.size = 0
scheduler.handler.size = 0
scheduler.cbRetData.size = 0
Simulation complete via $finish(1) at time 19995 NS + 0
./cadd_tb.v:20 $finish;
ncsim> exit
