doesn't the opencl notation in the 16x case require 16^16 orders to be supported (even if its implicit in the parser support?) That said, if it can be engineered in sane way, sure, that'd be neat, how does the OpenCL notation work in the 16x simd case?
On Thu, Jan 16, 2014 at 6:16 PM, Jens Nockert <j...@nockert.se> wrote: > > On 2014/01/17, at 0:12, Carter Schonwald <carter.schonw...@gmail.com> > wrote: > > > whatever the notation, it needs to be one that > > a) gives good support for enforcing the "the shuffle is dictated at > compile time" > > b) is really simple, and easy to adjust for different size SIMD vectors. > 2x, 4x,8x,16x are all ones that currently and/or will soon exist on the > CPU front at the very least! > > I prefer the OpenCL notation, vector.xyzw, vector.s0321 and so on. > Supports up to 16 elements, which is fine with most common SIMD types. > (AVX-512 with bytes and so on will always require horrible syntax, since > there are so many elements)
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