Edwin Blink wrote: > From: Geoff Winkless <[EMAIL PROTECTED]> > >> Trying to think this through... > > Like the Idea. So I looked a bit better at LDIR in ROM too. > > LDIR is made up of 5 M-cycles: > 4,4,3,5,5 for standard LDIR = 21T > 4,4,3+1,5,5+2 LDIR in RAM with RAM contemption = 24T > 4+4,4+4,3+5,5,5+6 LDIR in RAM with Display contemption = 40Ts > 4,4,3+1,5,5+2 LDIR in ROM with RAM contemption = 24Ts > 4,4,3+5,5,5+6 LDIR in ROM with Display contemption = 32Ts
Mmm. Makes sense. It's "contention", btw. Incidentally, what are the 5 cycles for an LDIR? Obviously 2 cycles to read the instruction, one to read and one to write. One of the 5's is evidently unused when (--BC)==0, so is it really the case that the z80 reads the (erroneous) next instruction before doing PC-=2 (as one source on the web suggested)? And if so, why 5 and not 4 (since reading EDBO is 4 each)? G ______________________________________________________________________ This email has been scanned by the MessageLabs Email Security System. For more information please visit http://www.messagelabs.com/email ______________________________________________________________________
