Has anyone done any work on this before I start randomly fiddling ?
Looking at the SDCC tree the gbz80 port actually appears to be pretty
close to what is needed for 8080 (asm mnemonics conventionally used are
different but the actual instruction set is) and also to generate
remarkably good code for such a limited CPU.
>From some initial scoping it seems that for Sdcc output the differences
that matter are
- no LD x , (HL+) or (HL-)
which is fine because they are semantically identical to the two
instruction sequence with the following INC (as INC 16bit doesn't touch
flags)
- 8080 has in/out
- no shortforum loads to 0xFFxx
not a big deal, as we don't have I/O in this way and Sdcc doesn't seem to
use them
- no LDHL SP, #n
becomes ld hl, #n
add hl, sp
I think
- no bit instructions and arbitrary register shifts (basically no CBxx)
Looks harder to deal with, particularly the top bit testing stuff. Any
shifts have to go through A, so the usually generated stuff for
rla (hl)
inc hl
rla (hl)
doesn't work but needs to be
ld a, (hl)
rla
ld (hl), a
inc hl
etc
ditto for bit operations, you end up with
ld a, (hl) ; or ld a, b
and 0x80
stuff so need a clear a lot more than a gbz80 or real Z80
- no swap r, (hl)
but fortunately I've not found that in any sdcc output 8)
- interrupt stuff is different
ret not iret, no way to stack the existing interrupt state from the
hardware (much like an NMOS Z80 in fact where ld a,i push af doesn't work
reliably).
And since its a strict subset of Z80, the Z80 assembler will do fine
Alan
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