On Sun, Dec 22, 2013 at 09:54:02PM -0500, Kevin O'Connor wrote: > On Fri, Dec 13, 2013 at 02:25:39PM -0500, Kevin O'Connor wrote: > > On Fri, Dec 13, 2013 at 01:27:45PM -0500, Kevin O'Connor wrote: > > > 01.342: xhci hcc=40050af hcs=4000440 > > > > > > I think this means that Context Size (CSZ) == 64 bytes and the > > > controller isn't compatible with the seabios driver? > > > > FYI, with the (incredibly ugly) patch below, I get a little further. > > FYI, with the (incredibly ugly) patch from the previous mail and with > a USB3 flash drive I seem to get slightly further.
FYI, it seems my USB3 controller really wants to see 64bit writes to pci registers. With the change below (on top of the other changes) I can now boot my e350m1 from a USB3 flash drive. I'm still seeing failures on my keyboard/mouse though: 01.146: XHCI port #2: 0x00200a03, powered, enabled, pls 0, speed 2 [Low] 01.163: xhci_control: control xfer failed (cc 6) and on my USB2 flash drive: 01.132: XHCI port #1: 0x00200e03, powered, enabled, pls 0, speed 3 [High] 01.163: xhci_update_pipe: reconf ctl endpoint pkt size: 8 -> 64 01.168: xhci_alloc_pipe: configure endpoint: failed (cc 17) 01.169: xhci_alloc_pipe: configure endpoint: failed (cc 17) 01.169: Unable to configure USB MSC device. -Kevin diff --git a/src/hw/usb-xhci.c b/src/hw/usb-xhci.c index dc98e5d..d0df6ee 100644 --- a/src/hw/usb-xhci.c +++ b/src/hw/usb-xhci.c @@ -379,6 +379,7 @@ static void xhci_process_events(struct usb_xhci_s *xhci) u32 addr = (u32)(&ir->erdp_low); u32 erdp = (u32)(evts->ring + nidx); pci_writel(addr, erdp); + pci_writel((u32)(&ir->erdp_high), 0); } } _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org http://www.seabios.org/mailman/listinfo/seabios