On Sun, Mar 08, 2015 at 01:16:15PM +0200, Marcel Apfelbaum wrote:
> If multiple root busses are used, root bus 0 cannot use all the
> pci holes ranges. Remove the IO/mem ranges used by the other
> primary busses.
[...]
> - aml_append(crs,
> - aml_word_io(aml_min_fixed, aml_max_fixed,
> - aml_pos_decode, aml_entire_range,
> - 0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300));
> +
> + /* prepare PCI IO ranges */
> + range.base = 0x0D00;
> + range.limit = 0xFFFF;
> + if (QLIST_EMPTY(&io_ranges)) {
> + aml_append(crs,
> + aml_word_io(aml_min_fixed, aml_max_fixed,
> + aml_pos_decode, aml_entire_range,
> + 0x0000, range.base, range.limit,
> + 0x0000, range.limit - range.base + 1));
> + } else {
> + QLIST_FOREACH(entry, &io_ranges, entry) {
> + if (range.base < entry->base) {
> + aml_append(crs,
> + aml_word_io(aml_min_fixed, aml_max_fixed,
> + aml_pos_decode, aml_entire_range,
> + 0x0000, range.base, entry->base - 1,
> + 0x0000, entry->base - range.base));
> + }
> + range.base = entry->limit + 1;
> + if (!QLIST_NEXT(entry, entry)) {
> + aml_append(crs,
> + aml_word_io(aml_min_fixed, aml_max_fixed,
> + aml_pos_decode, aml_entire_range,
> + 0x0000, range.base, range.limit,
> + 0x0000, range.limit - range.base + 1));
> + }
> + }
> + }
If I read this correctly, it looks like a machine with two root buses
and 20 devices, each with one memory range and one io range, would end
up with 40 CRS ranges (ie, a CRS range for every resource). It also
looks like this furthers the requirement that the guest firmware
assign the PCI resources prior to QEMU being able to generate the ACPI
tables.
Am I correct? If so, that doesn't sound ideal.
-Kevin
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