On 03/06/2018 11:04 AM, Paul Menzel wrote:
Dear Stephen, dear Kevin,
On 03/02/18 17:31, Kevin O'Connor wrote:
On Tue, Feb 27, 2018 at 02:17:08PM -0500, Stephen Douthit wrote:
[…]
Thanks. I committed this series.
The second commit introduced a regression with coreboot on the ASRock E350M1.
There are a bunch of time-outs, causing the startup to be really slow. With no
serial console, the user thinks, it’s not working and start to debug.
Looking through the the user manual for that board I don't see that it
has a TPM, or even the header for one, so a timeout seems correct.
Multiple 750ms timeouts does seem pretty painful though. I hadn't
considered that tis_probe() would be called multiple times if no TPM
was present.
What's the preferred way to have a probe function run and bail before
rerunning the timeout? Just put a static flag in tis_probe()? The
attached patch takes that approach. Please let me know if that fixes
the issue for you, or if there's some other preferred pattern I should
use here.
Thanks,
Steve
```
[…]
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 75840 size 10bfc
Loading segment from ROM address 0xffc75a78
code (compression=1)
New segment dstaddr 0xe0200 memsize 0x1fe00 srcaddr 0xffc75ab0 filesize
0x10bc4
Loading segment from ROM address 0xffc75a94
Entry Point 0x000fd23d
Loading Segment: addr: 0x00000000000e0200 memsz: 0x000000000001fe00 filesz:
0x0000000000010bc4
lb: [0x00000000c7eb3000, 0x00000000c7fb5730)
Post relocation: addr: 0x00000000000e0200 memsz: 0x000000000001fe00 filesz:
0x0000000000010bc4
using LZMA
[ 0x000e0200, 00100000, 0x00100000) <- ffc75ab0
dest 000e0200, end 00100000, bouncebuffer ffffffff
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 95671 exit 0
Jumping to boot code at 000fd23d(c7d77000)
CPU0: stack: c7eef000 - c7ef0000, lowest used address c7eef6ac, stack used:
2388 bytes
SeaBIOS (version rel-1.11.0-25-g5adc8bd)
BUILD: gcc: (coreboot toolchain v1.50 October 15th, 2017) 6.3.0 binutils: (GNU
Binutils) 2.29.1
SeaBIOS (version rel-1.11.0-25-g5adc8bd)
BUILD: gcc: (coreboot toolchain v1.50 October 15th, 2017) 6.3.0 binutils: (GNU
Binutils) 2.29.1
Found coreboot cbmem console @ c7fde000
Found mainboard ASROCK E350M1
Relocating init from 0x000e1840 to 0xc7cf32e0 (size 52352)
Found CBFS header at 0xffc00238
multiboot: eax=c7eeab60, ebx=c7eeab14
Found 24 PCI devices (max PCI bus is 03)
Copying SMBIOS entry point from 0xc7d40000 to 0x000f6120
Copying ACPI RSDP from 0xc7d51000 to 0x000f60f0
Copying MPTABLE from 0xc7d75000/c7d75010 to 0x000f5ef0
Copying PIR from 0xc7d76000 to 0x000f5ec0
Using pmtimer, ioport 0x808
WARNING - Timeout at wait_reg8:81!
WARNING - Timeout at wait_reg8:81!
WARNING - Timeout at wait_reg8:81!
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga text mode console
SeaBIOS (version rel-1.11.0-25-g5adc8bd)
EHCI init on dev 00:12.2 (regs=0xf014c020)
EHCI init on dev 00:13.2 (regs=0xf014d020)
OHCI init on dev 00:12.0 (regs=0xf0148000)
OHCI init on dev 00:13.0 (regs=0xf0149000)
OHCI init on dev 00:14.5 (regs=0xf014a000)
AHCI controller at 00:11.0, iobase 0xf014b000, irq 0
Found 0 lpt ports
Found 1 serial ports
Searching bootorder for: /rom@img/memtest
Searching bootorder for: /rom@img/tint
Searching bootorder for: /rom@img/nvramcui
Searching bootorder for: /rom@img/coreinfo
USB mouse initialized
PS2 keyboard initialized
All threads complete.
Scan for option roms
Press ESC for boot menu.
WARNING - Timeout at wait_reg8:81!
```
Please find the config file attached.
Is it possible to add better error handling? Or should this option better be
disable by default for people running `make olddefconfig`.
Kind regards,
Paul
>From 5a8ddac44da4ff68861e23ada5bf15a307076db2 Mon Sep 17 00:00:00 2001
From: Stephen Douthit <steph...@silicom-usa.com>
Date: Tue, 6 Mar 2018 11:52:20 -0500
Subject: [PATCH] tpm: Save tis_probe() result to avoid a reun of lengthy
timeouts
Signed-off-by: Stephen Douthit <steph...@silicom-usa.com>
---
src/hw/tpm_drivers.c | 23 ++++++++++++++++++-----
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/src/hw/tpm_drivers.c b/src/hw/tpm_drivers.c
index ed58bf5..e1eb441 100644
--- a/src/hw/tpm_drivers.c
+++ b/src/hw/tpm_drivers.c
@@ -63,6 +63,8 @@ static void *crb_cmd;
static u32 crb_resp_size;
static void *crb_resp;
+static u32 tis_probe_failed = 0;
+
static u32 wait_reg8(u8* reg, u32 time, u8 mask, u8 expect)
{
if (!CONFIG_TCGBIOS)
@@ -107,17 +109,26 @@ static u32 tis_probe(void)
if (!CONFIG_TCGBIOS)
return 0;
+ /*
+ * The timeout if no TPM is present is fairly long, don't slow the boot if
+ * we've determined there's no part present
+ */
+ if (tis_probe_failed)
+ return 0;
+
/* Wait for the interface to report it's ready */
- u32 rc = tis_wait_access(0, TIS_DEFAULT_TIMEOUT_A,
+ tis_probe_failed = tis_wait_access(0, TIS_DEFAULT_TIMEOUT_A,
TIS_ACCESS_TPM_REG_VALID_STS,
TIS_ACCESS_TPM_REG_VALID_STS);
- if (rc)
+ if (tis_probe_failed)
return 0;
u32 didvid = readl(TIS_REG(0, TIS_REG_DID_VID));
- if ((didvid != 0) && (didvid != 0xffffffff))
- rc = 1;
+ if ((didvid == 0) || (didvid == 0xffffffff)) {
+ tis_probe_failed = 1;
+ return 0;
+ }
/* TPM 2 has an interface register */
u32 ifaceid = readl(TIS_REG(0, TIS_REG_IFACE_ID));
@@ -125,10 +136,12 @@ static u32 tis_probe(void)
if ((ifaceid & 0xf) != 0xf) {
if ((ifaceid & 0xf) == 1) {
/* CRB is active; no TIS */
+ tis_probe_failed = 1;
return 0;
}
if ((ifaceid & (1 << 13)) == 0) {
/* TIS cannot be selected */
+ tis_probe_failed = 1;
return 0;
}
/* write of 0 to bits 17-18 selects TIS */
@@ -137,7 +150,7 @@ static u32 tis_probe(void)
writel(TIS_REG(0, TIS_REG_IFACE_ID), (1 << 19));
}
- return rc;
+ return 1;
}
static TPMVersion tis_get_tpm_version(void)
--
2.14.3
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