Dear SeaBIOS folks,
On the laptop TUXEDO Book BU1406 (Clevo N240BU) with coreboot [1] and
SeaBIOS master, the internal PS/2 keyboard often does not work.
SeaBIOS (version rel-1.13.0-45-g6ada228)
[…]
/7aa38000\ Start thread
|7aa38000| Discarding ps2 data 41 (status=13)
Searching bootorder for: HALT
/7aa35000\ Start thread
Found 0 lpt ports
Found 0 serial ports
|7aa38000| keyboard self test failed (got ab not 0xaa)
\7aa38000/ End thread
[…]
Kind regards,
Paul
[1]: https://review.coreboot.org/c/coreboot/+/43760/
"mb/clevo/kbl-u: Add Clevo N240BU as variant"
coreboot-4.12-1645-gb17feaaee0 Sat Jul 25 09:17:46 UTC 2020 bootblock starting
(log level: 7)...
CPU: Intel(R) Core(TM) i7-7500U CPU @ 2.70GHz
CPU: ID 806e9, Kabylake H0, ucode: 000000c9
CPU: AES supported, TXT NOT supported, VT supported
MCH: device id 5904 (rev 02) is Kabylake-U
PCH: device id 9d4e (rev 21) is Kabylake-U iHDCP 2.2 Premium
IGD: device id 5916 (rev 02) is Kaby Lake ULT GT2
FMAP: area COREBOOT found @ 350200 (4914688 bytes)
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 80 size b3dc
BS: bootblock times (exec / console): total (unknown) / 1 ms
coreboot-4.12-1645-gb17feaaee0 Sat Jul 25 09:17:46 UTC 2020 romstage starting
(log level: 7)...
pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00000000
gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
TCO_STS: 0000 0000
GEN_PMCON: e0040200 0000507a
GBLRST_CAUSE: 00000000 00000000
prev_sleep_state 5
FMAP: area COREBOOT found @ 350200 (4914688 bytes)
CBFS: Locating 'fspm.bin'
CBFS: Found @ offset 70dc0 size 63000
FMAP: area RW_MRC_CACHE found @ 340000 (65536 bytes)
PRMRR disabled by config.
mainboard_memory_init_params: Begin functionSPD @ 0x50
SPD: module type is DDR4
SPD: module part number is BLS16G4S240FSD.16FBD
SPD: banks 16, ranks 2, rows 16, columns 10, density 8192 Mb
SPD: device width 8 bits, bus width 64 bits
SPD: module size is 16384 MB (per channel)
SPD @ 0x52
SPD: module type is DDR4
SPD: module part number is BLS16G4S240FSD.16FBD
SPD: banks 16, ranks 2, rows 16, columns 10, density 8192 Mb
SPD: device width 8 bits, bus width 64 bits
SPD: module size is 16384 MB (per channel)
mainboard_memory_init_params: End functionCBMEM:
IMD: root @ 0x7afff000 254 entries.
IMD: root @ 0x7affec00 62 entries.
External stage cache:
IMD: root @ 0x7b3ff000 254 entries.
IMD: root @ 0x7b3fec00 62 entries.
2 DIMMs found
SMM Memory Map
SMRAM : 0x7b000000 0x800000
Subregion 0: 0x7b000000 0x200000
Subregion 1: 0x7b200000 0x200000
Subregion 2: 0x7b400000 0x400000
top_of_ram = 0x7b000000
MTRR Range: Start=7a000000 End=7b000000 (Size 1000000)
MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
MTRR Range: Start=ff800000 End=0 (Size 800000)
FMAP: area COREBOOT found @ 350200 (4914688 bytes)
CBFS: Locating 'fallback/postcar'
CBFS: Found @ offset 112e80 size 785c
Decompressing stage fallback/postcar @ 0x7abcdfc0 (46360 bytes)
Loading module at 0x7abce000 with entry 0x7abce000. filesize: 0x7110 memsize:
0xb4d8
Processing 444 relocs. Offset value of 0x78bce000
BS: romstage times (exec / console): total (unknown) / 4 ms
coreboot-4.12-1645-gb17feaaee0 Sat Jul 25 09:17:46 UTC 2020 postcar starting
(log level: 7)...
FMAP: area COREBOOT found @ 350200 (4914688 bytes)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 54d40 size 17f60
Decompressing stage fallback/ramstage @ 0x7ab08fc0 (801776 bytes)
Loading module at 0x7ab09000 with entry 0x7ab09000. filesize: 0x32330 memsize:
0xc3bb0
Processing 3344 relocs. Offset value of 0x79d09000
BS: postcar times (exec / console): total (unknown) / 1 ms
coreboot-4.12-1645-gb17feaaee0 Sat Jul 25 09:17:46 UTC 2020 ramstage starting
(log level: 7)...
Normal boot
FMAP: area COREBOOT found @ 350200 (4914688 bytes)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset b4c0 size 49800
microcode: sig=0x806e9 pf=0x80 revision=0xc9
Skip microcode update
FMAP: area COREBOOT found @ 350200 (4914688 bytes)
CBFS: Locating 'fsps.bin'
CBFS: Found @ offset d4dc0 size 2e000
Detected 2 core, 4 thread CPU.
Setting up SMI for CPU
IED base = 0x7b400000
IED size = 0x00400000
Will perform SMM setup.
CPU: Intel(R) Core(TM) i7-7500U CPU @ 2.70GHz.
Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize:
0x170
Processing 16 relocs. Offset value of 0x00030000
Attempting to start 3 APs
Waiting for 10ms after sending INIT.
Waiting for 1st SIPI to complete...AP: slot 2 apic_id 1.
done.
AP: slot 3 apic_id 2.
AP: slot 1 apic_id 3.
Waiting for 2nd SIPI to complete...done.
Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize:
0x1b8
Processing 13 relocs. Offset value of 0x00038000
Unable to locate Global NVS
SMM Module: stub loaded at 0x00038000. Will call 0x7ab20e0f(0x00000000)
Installing SMM handler to 0x7b000000
Loading module at 0x7b010000 with entry 0x7b01008e. filesize: 0x2508 memsize:
0x6520
Processing 256 relocs. Offset value of 0x7b010000
Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize:
0x1b8
Processing 13 relocs. Offset value of 0x7b008000
SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
Unable to locate Global NVS
SMM Module: stub loaded at 0x7b008000. Will call 0x7b01008e(0x00000000)
Clearing SMI status registers
SMI_STS: PM1
PWRBTN New SMBASE 0x7b000000
In relocation handler: CPU 0
New SMBASE=0x7b000000 IEDBASE=0x7b400000
Writing SMRR. base = 0x7b000006, mask=0xff800800
Relocation complete.
New SMBASE 0x7afff800
In relocation handler: CPU 2
New SMBASE=0x7afff800 IEDBASE=0x7b400000
Writing SMRR. base = 0x7b000006, mask=0xff800800
Relocation complete.
New SMBASE 0x7afffc00
In relocation handler: CPU 1
New SMBASE=0x7afffc00 IEDBASE=0x7b400000
Writing SMRR. base = 0x7b000006, mask=0xff800800
Relocation complete.
New SMBASE 0x7afff400
In relocation handler: CPU 3
New SMBASE=0x7afff400 IEDBASE=0x7b400000
Writing SMRR. base = 0x7b000006, mask=0xff800800
Relocation complete.
Initializing CPU #0
CPU: vendor Intel device 806e9
CPU: family 06, model 8e, stepping 09
Clearing out pending MCEs
Setting up local APIC...
apic_id: 0x00 done.
cpu: energy policy set to 6
Turbo is available but hidden
Turbo is available and visible
Skip microcode update
CPU #0 initialized
Initializing CPU #2
Initializing CPU #3
Initializing CPU #1
CPU: vendor Intel device 806e9
CPU: family 06, model 8e, stepping 09
CPU: vendor Intel device 806e9
CPU: family 06, model 8e, stepping 09
Clearing out pending MCEs
Clearing out pending MCEs
Setting up local APIC...
CPU: vendor Intel device 806e9
CPU: family 06, model 8e, stepping 09
Clearing out pending MCEs
Setting up local APIC...
Setting up local APIC...
apic_id: 0x02 done.
apic_id: 0x03 done.
cpu: energy policy set to 6
cpu: energy policy set to 6
Skip microcode update
CPU #3 initialized
Skip microcode update
CPU #1 initialized
apic_id: 0x01 done.
cpu: energy policy set to 6
Skip microcode update
CPU #2 initialized
bsp_do_flight_plan done after 7 msecs.
CPU: frequency set to 3500 MHz
Enabling SMIs.
Locking SMM.
VMX status: enabled
VMX status: enabled
IA32_FEATURE_CONTROL status: locked
VMX status: enabled
VMX status: enabled
IA32_FEATURE_CONTROL status: locked
IA32_FEATURE_CONTROL status: locked
IA32_FEATURE_CONTROL status: locked
BS: BS_DEV_INIT_CHIPS entry times (exec / console): 78 / 4 ms
mainboard_silicon_init_params: Begin functiongpio_pad_reset_config_override:
Logical to Chipset mapping not found
gpio_pad_reset_config_override: Logical to Chipset mapping not found
gpio_pad_reset_config_override: Logical to Chipset mapping not found
gpio_pad_reset_config_override: Logical to Chipset mapping not found
mainboard_silicon_init_params: End functionITSS IRQ Polarities Before:
IPC0: 0x00ff4000
IPC1: 0x00000007
IPC2: 0x00000000
IPC3: 0x00000000
ITSS IRQ Polarities After:
IPC0: 0x00ff4000
IPC1: 0x00000007
IPC2: 0x00000000
IPC3: 0x00000000
Found PCIe Root Port #1 at PCI: 00:1c.0.
Found PCIe Root Port #6 at PCI: 00:1c.5.
Found PCIe Root Port #9 at PCI: 00:1d.0.
pcie_rp_update_dev: Couldn't find PCIe Root Port #5 (originally PCI: 00:1c.4)
which was enabled in devicetree, removing.
BS: BS_DEV_INIT_CHIPS run times (exec / console): 136 / 2 ms
Enumerating buses...
Root Device scanning...
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/5904] enabled
PCI: 00:02.0 [8086/5916] enabled
PCI: 00:04.0 [8086/1903] enabled
PCI: 00:14.0 [8086/9d2f] enabled
PCI: 00:14.2 [8086/9d31] enabled
PCI: 00:16.0 [8086/9d3a] disabled
PCI: 00:17.0 [8086/9d03] enabled
PCI: 00:1c.0 [8086/9d10] enabled
PCI: 00:1c.5 [8086/9d15] enabled
PCI: 00:1d.0 [8086/9d18] enabled
PCI: 00:1f.0 [8086/9d4e] enabled
PCI: 00:1f.1 [8086/9d20] disabled
PCI: 00:1f.2 [8086/9d21] enabled
PCI: 00:1f.3 [8086/9d71] enabled
PCI: 00:1f.4 [8086/9d23] enabled
PCI: 00:1f.5 [8086/9d24] enabled
PCI: Leftover static devices:
PCI: 00:08.0
PCI: 00:16.1
PCI: 00:16.2
PCI: 00:16.3
PCI: 00:16.4
PCI: 00:1f.6
PCI: Check your devicetree.cb.
PCI: 00:02.0 scanning...
scan_bus: bus PCI: 00:02.0 finished in 0 msecs
PCI: 00:14.0 scanning...
scan_bus: bus PCI: 00:14.0 finished in 0 msecs
PCI: 00:1c.0 scanning...
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [1b21/1242] enabled
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled None
PCIe: Max_Payload_Size adjusted to 128
scan_bus: bus PCI: 00:1c.0 finished in 1 msecs
PCI: 00:1c.5 scanning...
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [10ec/5287] enabled
PCI: 02:00.1 [10ec/8168] enabled
Enabling Common Clock Configuration
L1 Sub-State supported from root port 28
L1 Sub-State Support = 0xf
CommonModeRestoreTime = 0x96
Power On Value = 0xf, Power On Scale = 0x1
ASPM: Enabled L1
PCIe: Max_Payload_Size adjusted to 128
Enabling Common Clock Configuration
ASPM: Enabled L1
PCIe: Max_Payload_Size adjusted to 128
scan_bus: bus PCI: 00:1c.5 finished in 2 msecs
PCI: 00:1d.0 scanning...
PCI: pci_scan_bus for bus 03
PCI: 03:00.0 [144d/a804] enabled
Enabling Common Clock Configuration
L1 Sub-State supported from root port 29
L1 Sub-State Support = 0xf
CommonModeRestoreTime = 0x28
Power On Value = 0x16, Power On Scale = 0x0
ASPM: Enabled L1
PCIe: Max_Payload_Size adjusted to 128
scan_bus: bus PCI: 00:1d.0 finished in 1 msecs
PCI: 00:1f.0 scanning...
PNP: 0c31.0 enabled
scan_bus: bus PCI: 00:1f.0 finished in 0 msecs
PCI: 00:1f.2 scanning...
scan_bus: bus PCI: 00:1f.2 finished in 0 msecs
PCI: 00:1f.3 scanning...
scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
PCI: 00:1f.4 scanning...
scan_bus: bus PCI: 00:1f.4 finished in 0 msecs
PCI: 00:1f.5 scanning...
scan_bus: bus PCI: 00:1f.5 finished in 0 msecs
scan_bus: bus DOMAIN: 0000 finished in 12 msecs
scan_bus: bus Root Device finished in 12 msecs
done
BS: BS_DEV_ENUMERATE run times (exec / console): 2 / 11 ms
FMAP: area RW_MRC_CACHE found @ 340000 (65536 bytes)
MRC: Checking cached data update for 'RW_MRC_CACHE'.
MRC: 'RW_MRC_CACHE' does not need update.
MRC: Could not find region 'UNIFIED_MRC_CACHE'
FMAP: area RW_MRC_CACHE found @ 340000 (65536 bytes)
MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
BS: BS_DEV_ENUMERATE exit times (exec / console): 3 / 1 ms
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Done reading resources.
==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 10 * [0x0 - 0x7fff] mem
PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.5 io: size: 0 align: 12 gran: 12 limit: ffff
PCI: 02:00.1 10 * [0x0 - 0xff] io
PCI: 00:1c.5 io: size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.5 mem: size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.0 30 * [0x0 - 0xffff] mem
PCI: 02:00.1 20 * [0x10000 - 0x13fff] mem
PCI: 02:00.0 10 * [0x14000 - 0x14fff] mem
PCI: 02:00.1 18 * [0x15000 - 0x15fff] mem
PCI: 00:1c.5 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.5 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.5 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:00.0 10 * [0x0 - 0x3fff] mem
PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
=== Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
update_constraints: PCI: 00:1f.2 40 base 00001800 limit 000018ff io (fixed)
update_constraints: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
DOMAIN: 0000: Resource ranges:
* Base: 1000, Size: 800, Tag: 100
* Base: 1900, Size: d6a0, Tag: 100
* Base: efc0, Size: 1040, Tag: 100
PCI: 00:1c.5 1c * [0x2000 - 0x2fff] limit: 2fff io
PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
PCI: 00:17.0 20 * [0x1040 - 0x105f] limit: 105f io
PCI: 00:17.0 18 * [0x1060 - 0x1067] limit: 1067 io
PCI: 00:17.0 1c * [0x1068 - 0x106b] limit: 106b io
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
update_constraints: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
update_constraints: PCI: 00:00.0 01 base fed10000 limit fed17fff mem (fixed)
update_constraints: PCI: 00:00.0 02 base fed18000 limit fed18fff mem (fixed)
update_constraints: PCI: 00:00.0 03 base fed19000 limit fed19fff mem (fixed)
update_constraints: PCI: 00:00.0 04 base fed84000 limit fed84fff mem (fixed)
update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
update_constraints: PCI: 00:00.0 07 base fed91000 limit fed91fff mem (fixed)
update_constraints: PCI: 00:00.0 08 base 00000000 limit 0009ffff mem (fixed)
update_constraints: PCI: 00:00.0 09 base 000c0000 limit 7affffff mem (fixed)
update_constraints: PCI: 00:00.0 0a base 7b000000 limit 7b7fffff mem (fixed)
update_constraints: PCI: 00:00.0 0b base 7b800000 limit 7fffffff mem (fixed)
update_constraints: PCI: 00:00.0 0c base 100000000 limit 87effffff mem (fixed)
update_constraints: PCI: 00:00.0 0d base 000a0000 limit 000bffff mem (fixed)
update_constraints: PCI: 00:00.0 0e base 000c0000 limit 000fffff mem (fixed)
update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
update_constraints: PCI: 00:1f.2 48 base fe000000 limit fe00ffff mem (fixed)
DOMAIN: 0000: Resource ranges:
* Base: 80000000, Size: 60000000, Tag: 200
* Base: f0000000, Size: e000000, Tag: 200
* Base: fe010000, Size: d00000, Tag: 200
* Base: fed1a000, Size: 26000, Tag: 200
* Base: fed45000, Size: 3b000, Tag: 200
* Base: fed85000, Size: b000, Tag: 200
* Base: fed92000, Size: 126e000, Tag: 200
* Base: 87f000000, Size: 7781000000, Tag: 100200
PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
PCI: 00:1c.0 20 * [0x91000000 - 0x910fffff] limit: 910fffff mem
PCI: 00:1c.5 20 * [0x91100000 - 0x911fffff] limit: 911fffff mem
PCI: 00:1d.0 20 * [0x91200000 - 0x912fffff] limit: 912fffff mem
PCI: 00:14.0 10 * [0x91300000 - 0x9130ffff] limit: 9130ffff mem
PCI: 00:1f.3 20 * [0x91310000 - 0x9131ffff] limit: 9131ffff mem
PCI: 00:04.0 10 * [0x91320000 - 0x91327fff] limit: 91327fff mem
PCI: 00:1f.2 10 * [0x91328000 - 0x9132bfff] limit: 9132bfff mem
PCI: 00:1f.3 10 * [0x9132c000 - 0x9132ffff] limit: 9132ffff mem
PCI: 00:17.0 10 * [0x91330000 - 0x91331fff] limit: 91331fff mem
PCI: 00:14.2 10 * [0x91332000 - 0x91332fff] limit: 91332fff mem
PCI: 00:1f.5 10 * [0x91333000 - 0x91333fff] limit: 91333fff mem
PCI: 00:17.0 24 * [0x91334000 - 0x913347ff] limit: 913347ff mem
PCI: 00:17.0 14 * [0x91335000 - 0x913350ff] limit: 913350ff mem
PCI: 00:1f.4 10 * [0x91336000 - 0x913360ff] limit: 913360ff mem
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
PCI: 00:1c.0 mem: base: 91000000 size: 100000 align: 20 gran: 20 limit: 910fffff
PCI: 00:1c.0: Resource ranges:
* Base: 91000000, Size: 100000, Tag: 200
PCI: 01:00.0 10 * [0x91000000 - 0x91007fff] limit: 91007fff mem
PCI: 00:1c.0 mem: base: 91000000 size: 100000 align: 20 gran: 20 limit:
910fffff done
PCI: 00:1c.5 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff
PCI: 00:1c.5: Resource ranges:
* Base: 2000, Size: 1000, Tag: 100
PCI: 02:00.1 10 * [0x2000 - 0x20ff] limit: 20ff io
PCI: 00:1c.5 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff done
PCI: 00:1c.5 mem: base: 91100000 size: 100000 align: 20 gran: 20 limit: 911fffff
PCI: 00:1c.5: Resource ranges:
* Base: 91100000, Size: 100000, Tag: 200
PCI: 02:00.0 30 * [0x91100000 - 0x9110ffff] limit: 9110ffff mem
PCI: 02:00.1 20 * [0x91110000 - 0x91113fff] limit: 91113fff mem
PCI: 02:00.0 10 * [0x91114000 - 0x91114fff] limit: 91114fff mem
PCI: 02:00.1 18 * [0x91115000 - 0x91115fff] limit: 91115fff mem
PCI: 00:1c.5 mem: base: 91100000 size: 100000 align: 20 gran: 20 limit:
911fffff done
PCI: 00:1d.0 mem: base: 91200000 size: 100000 align: 20 gran: 20 limit: 912fffff
PCI: 00:1d.0: Resource ranges:
* Base: 91200000, Size: 100000, Tag: 200
PCI: 03:00.0 10 * [0x91200000 - 0x91203fff] limit: 91203fff mem
PCI: 00:1d.0 mem: base: 91200000 size: 100000 align: 20 gran: 20 limit:
912fffff done
=== Resource allocator: DOMAIN: 0000 - resource allocation complete ===
PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c
prefmem64
PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
PCI: 00:04.0 10 <- [0x0091320000 - 0x0091327fff] size 0x00008000 gran 0x0f mem64
PCI: 00:14.0 10 <- [0x0091300000 - 0x009130ffff] size 0x00010000 gran 0x10 mem64
PCI: 00:14.2 10 <- [0x0091332000 - 0x0091332fff] size 0x00001000 gran 0x0c mem64
PCI: 00:17.0 10 <- [0x0091330000 - 0x0091331fff] size 0x00002000 gran 0x0d mem
PCI: 00:17.0 14 <- [0x0091335000 - 0x00913350ff] size 0x00000100 gran 0x08 mem
PCI: 00:17.0 18 <- [0x0000001060 - 0x0000001067] size 0x00000008 gran 0x03 io
PCI: 00:17.0 1c <- [0x0000001068 - 0x000000106b] size 0x00000004 gran 0x02 io
PCI: 00:17.0 20 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io
PCI: 00:17.0 24 <- [0x0091334000 - 0x00913347ff] size 0x00000800 gran 0x0b mem
PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus
01 io
PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000
gran 0x14 bus 01 prefmem
PCI: 00:1c.0 20 <- [0x0091000000 - 0x00910fffff] size 0x00100000 gran 0x14 bus
01 mem
PCI: 01:00.0 10 <- [0x0091000000 - 0x0091007fff] size 0x00008000 gran 0x0f mem64
PCI: 00:1c.5 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus
02 io
PCI: 00:1c.5 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000
gran 0x14 bus 02 prefmem
PCI: 00:1c.5 20 <- [0x0091100000 - 0x00911fffff] size 0x00100000 gran 0x14 bus
02 mem
PCI: 02:00.0 10 <- [0x0091114000 - 0x0091114fff] size 0x00001000 gran 0x0c mem
PCI: 02:00.0 30 <- [0x0091100000 - 0x009110ffff] size 0x00010000 gran 0x10 romem
PCI: 02:00.1 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 02:00.1 18 <- [0x0091115000 - 0x0091115fff] size 0x00001000 gran 0x0c mem64
PCI: 02:00.1 20 <- [0x0091110000 - 0x0091113fff] size 0x00004000 gran 0x0e mem64
PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus
03 io
PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000
gran 0x14 bus 03 prefmem
PCI: 00:1d.0 20 <- [0x0091200000 - 0x00912fffff] size 0x00100000 gran 0x14 bus
03 mem
PCI: 03:00.0 10 <- [0x0091200000 - 0x0091203fff] size 0x00004000 gran 0x0e mem64
PCI: 00:1f.2 10 <- [0x0091328000 - 0x009132bfff] size 0x00004000 gran 0x0e mem
PCI: 00:1f.3 10 <- [0x009132c000 - 0x009132ffff] size 0x00004000 gran 0x0e mem64
PCI: 00:1f.3 20 <- [0x0091310000 - 0x009131ffff] size 0x00010000 gran 0x10 mem64
PCI: 00:1f.4 10 <- [0x0091336000 - 0x00913360ff] size 0x00000100 gran 0x08 mem64
PCI: 00:1f.5 10 <- [0x0091333000 - 0x0091333fff] size 0x00001000 gran 0x0c mem
Done setting resources.
Done allocating resources.
BS: BS_DEV_RESOURCES run times (exec / console): 1 / 41 ms
Enabling resources...
PCI: 00:00.0 subsystem <- 1558/1313
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 1558/1313
PCI: 00:02.0 cmd <- 03
PCI: 00:04.0 cmd <- 02
PCI: 00:14.0 subsystem <- 1558/1313
PCI: 00:14.0 cmd <- 02
PCI: 00:14.2 subsystem <- 1558/1313
PCI: 00:14.2 cmd <- 02
PCI: 00:17.0 subsystem <- 1558/1313
PCI: 00:17.0 cmd <- 03
PCI: 00:1c.0 bridge ctrl <- 0013
PCI: 00:1c.0 subsystem <- 1558/1313
PCI: 00:1c.0 cmd <- 06
PCI: 00:1c.5 bridge ctrl <- 0013
PCI: 00:1c.5 subsystem <- 1558/1313
PCI: 00:1c.5 cmd <- 07
PCI: 00:1d.0 bridge ctrl <- 0013
PCI: 00:1d.0 subsystem <- 1558/1313
PCI: 00:1d.0 cmd <- 06
PCI: 00:1f.0 subsystem <- 1558/1313
PCI: 00:1f.0 cmd <- 07
PCI: 00:1f.2 subsystem <- 1558/1313
PCI: 00:1f.2 cmd <- 02
PCI: 00:1f.3 subsystem <- 1558/1313
PCI: 00:1f.3 cmd <- 02
PCI: 00:1f.4 subsystem <- 1558/1313
PCI: 00:1f.4 cmd <- 03
PCI: 00:1f.5 subsystem <- 1558/1313
PCI: 00:1f.5 cmd <- 406
PCI: 01:00.0 cmd <- 02
PCI: 02:00.0 cmd <- 02
PCI: 02:00.1 cmd <- 03
PCI: 03:00.0 cmd <- 02
done.
BS: BS_DEV_ENABLE run times (exec / console): 1 / 4 ms
HECI: No CSE device
Found TPM SLB9665 TT 2.0 by Infineon
tlcl_send_startup: Startup return code is 0
TPM: setup succeeded
BS: BS_DEV_INIT entry times (exec / console): 8 / 0 ms
Initializing devices...
PCI: 00:00.0 init
CPU TDP = 15 Watts
CPU PL1 = 25 Watts
CPU PL2 = 44 Watts
PCI: 00:00.0 init finished in 1 msecs
PCI: 00:02.0 init
FMAP: area COREBOOT found @ 350200 (4914688 bytes)
CBFS: Locating 'vbt.bin'
CBFS: Found @ offset 6fc80 size 4a3
Found a VBT of 6144 bytes after decompression
GMA: Found VBT in CBFS
GMA: Found valid VBT in CBFS
PCI: 00:02.0 init finished in 2 msecs
PCI: 00:04.0 init
PCI: 00:04.0 init finished in 0 msecs
PCI: 00:14.0 init
PCI: 00:14.0 init finished in 0 msecs
PCI: 00:14.2 init
PCI: 00:14.2 init finished in 0 msecs
PCI: 00:17.0 init
PCI: 00:17.0 init finished in 0 msecs
PCI: 00:1c.0 init
Initializing PCH PCIe bridge.
PCI: 00:1c.0 init finished in 0 msecs
PCI: 00:1c.5 init
Initializing PCH PCIe bridge.
PCI: 00:1c.5 init finished in 0 msecs
PCI: 00:1d.0 init
Initializing PCH PCIe bridge.
PCI: 00:1d.0 init finished in 0 msecs
PCI: 00:1f.0 init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
PCI: 00:1f.0 init finished in 0 msecs
PCI: 00:1f.2 init
RTC Init
Set power on after power failure.
Disabling ACPI via APMC.
APMC done.
Disabling Deep S3
Disabling Deep S3
Disabling Deep S4
Disabling Deep S4
Disabling Deep S5
Disabling Deep S5
PCI: 00:1f.2 init finished in 1 msecs
PCI: 00:1f.3 init
HDA: codec_mask = 05
HDA: Initializing codec #2
HDA: codec viddid: 8086280b
HDA: verb loaded.
HDA: Initializing codec #0
HDA: codec viddid: 10ec0269
HDA: verb loaded.
PCI: 00:1f.3 init finished in 6 msecs
PCI: 00:1f.4 init
PCI: 00:1f.4 init finished in 0 msecs
PCI: 01:00.0 init
PCI: 01:00.0 init finished in 0 msecs
PCI: 02:00.0 init
PCI: 02:00.0 init finished in 0 msecs
PCI: 02:00.1 init
PCI: 02:00.1 init finished in 0 msecs
PCI: 03:00.0 init
PCI: 03:00.0 init finished in 0 msecs
Devices initialized
BS: BS_DEV_INIT run times (exec / console): 8 / 9 ms
Finalize devices...
Devices finalized
FMAP: area COREBOOT found @ 350200 (4914688 bytes)
CBFS: Locating 'fallback/dsdt.aml'
CBFS: Found @ offset 6d2c0 size 296e
FMAP: area COREBOOT found @ 350200 (4914688 bytes)
CBFS: Locating 'fallback/slic'
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at 7aa9c000.
ACPI: * FACS
ACPI: * DSDT
PCI space above 4GB MMIO is at 0x87f000000, len = 0x7781000000
ACPI: * FADT
SCI is IRQ9
ACPI: added table 1/32, length now 40
ACPI: * SSDT
Found 1 CPU(s) with 4 core(s) each.
PSS: 2701MHz power 15000 control 0x2300 status 0x2300
PSS: 2700MHz power 15000 control 0x1b00 status 0x1b00
PSS: 2500MHz power 13555 control 0x1900 status 0x1900
PSS: 2200MHz power 11514 control 0x1600 status 0x1600
PSS: 1900MHz power 9606 control 0x1300 status 0x1300
PSS: 1600MHz power 7796 control 0x1000 status 0x1000
PSS: 1300MHz power 6111 control 0xd00 status 0xd00
PSS: 1000MHz power 4528 control 0xa00 status 0xa00
PSS: 700MHz power 3049 control 0x700 status 0x700
PSS: 400MHz power 1676 control 0x400 status 0x400
PSS: 2701MHz power 15000 control 0x2300 status 0x2300
PSS: 2700MHz power 15000 control 0x1b00 status 0x1b00
PSS: 2500MHz power 13555 control 0x1900 status 0x1900
PSS: 2200MHz power 11514 control 0x1600 status 0x1600
PSS: 1900MHz power 9606 control 0x1300 status 0x1300
PSS: 1600MHz power 7796 control 0x1000 status 0x1000
PSS: 1300MHz power 6111 control 0xd00 status 0xd00
PSS: 1000MHz power 4528 control 0xa00 status 0xa00
PSS: 700MHz power 3049 control 0x700 status 0x700
PSS: 400MHz power 1676 control 0x400 status 0x400
PSS: 2701MHz power 15000 control 0x2300 status 0x2300
PSS: 2700MHz power 15000 control 0x1b00 status 0x1b00
PSS: 2500MHz power 13555 control 0x1900 status 0x1900
PSS: 2200MHz power 11514 control 0x1600 status 0x1600
PSS: 1900MHz power 9606 control 0x1300 status 0x1300
PSS: 1600MHz power 7796 control 0x1000 status 0x1000
PSS: 1300MHz power 6111 control 0xd00 status 0xd00
PSS: 1000MHz power 4528 control 0xa00 status 0xa00
PSS: 700MHz power 3049 control 0x700 status 0x700
PSS: 400MHz power 1676 control 0x400 status 0x400
PSS: 2701MHz power 15000 control 0x2300 status 0x2300
PSS: 2700MHz power 15000 control 0x1b00 status 0x1b00
PSS: 2500MHz power 13555 control 0x1900 status 0x1900
PSS: 2200MHz power 11514 control 0x1600 status 0x1600
PSS: 1900MHz power 9606 control 0x1300 status 0x1300
PSS: 1600MHz power 7796 control 0x1000 status 0x1000
PSS: 1300MHz power 6111 control 0xd00 status 0xd00
PSS: 1000MHz power 4528 control 0xa00 status 0xa00
PSS: 700MHz power 3049 control 0x700 status 0x700
PSS: 400MHz power 1676 control 0x400 status 0x400
\_SB.PCI0.LPCB.TPM.TPM: LPC TPM PNP: 0c31.0
ACPI: added table 2/32, length now 44
ACPI: * MCFG
ACPI: added table 3/32, length now 48
ACPI: * TPM2
TPM2 log created at 0x7aa8b000
ACPI: added table 4/32, length now 52
ACPI: * MADT
SCI is IRQ9
ACPI: added table 5/32, length now 56
current = 7aa9fd30
ACPI: * DMAR
ACPI: added table 6/32, length now 60
acpi_write_dbg2_pci_uart: Device not found
ACPI: * HPET
ACPI: added table 7/32, length now 64
ACPI: done.
ACPI tables: 15872 bytes.
smbios_write_tables: 7aa8a000
SMBIOS firmware version is set to coreboot_version: '4.12-1645-gb17feaaee0'
Create SMBIOS type 17
PCI: 00:00.0 (Intel 6th Gen)
SMBIOS tables: 780 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 8532
Writing coreboot table at 0x7aac0000
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-000000007aa89fff: RAM
4. 000000007aa8a000-000000007ab08fff: CONFIGURATION TABLES
5. 000000007ab09000-000000007abccfff: RAMSTAGE
6. 000000007abcd000-000000007affffff: CONFIGURATION TABLES
7. 000000007b000000-000000007fffffff: RESERVED
8. 00000000e0000000-00000000efffffff: RESERVED
9. 00000000fe000000-00000000fe00ffff: RESERVED
10. 00000000fed10000-00000000fed19fff: RESERVED
11. 00000000fed40000-00000000fed44fff: RESERVED
12. 00000000fed80000-00000000fed84fff: RESERVED
13. 00000000fed90000-00000000fed91fff: RESERVED
14. 0000000100000000-000000087effffff: RAM
FMAP: area COREBOOT found @ 350200 (4914688 bytes)
Wrote coreboot table at: 0x7aac0000, 0x454 bytes, checksum f59b
coreboot table: 1132 bytes.
IMD ROOT 0. 0x7afff000 0x00001000
IMD SMALL 1. 0x7affe000 0x00001000
FSP MEMORY 2. 0x7abfe000 0x00400000
CONSOLE 3. 0x7abde000 0x00020000
TIME STAMP 4. 0x7abdd000 0x00000910
MRC DATA 5. 0x7abdb000 0x00001878
ROMSTG STCK 6. 0x7abda000 0x00001000
AFTER CAR 7. 0x7abcd000 0x0000d000
RAMSTAGE 8. 0x7ab08000 0x000c5000
REFCODE 9. 0x7aada000 0x0002e000
SMM BACKUP 10. 0x7aaca000 0x00010000
4f444749 11. 0x7aac8000 0x00002000
COREBOOT 12. 0x7aac0000 0x00008000
ACPI 13. 0x7aa9c000 0x00024000
ACPI GNVS 14. 0x7aa9b000 0x00001000
TPM2 TCGLOG15. 0x7aa8b000 0x00010000
SMBIOS 16. 0x7aa8a000 0x00000800
IMD small region:
IMD ROOT 0. 0x7affec00 0x00000400
FSP RUNTIME 1. 0x7affebe0 0x00000004
FMAP 2. 0x7affeac0 0x0000010a
POWER STATE 3. 0x7affea80 0x00000040
ROMSTAGE 4. 0x7affea60 0x00000004
MEM INFO 5. 0x7affe8a0 0x000001b9
BS: BS_WRITE_TABLES run times (exec / console): 4 / 24 ms
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x000000007b800000 size 0x7b740000 type 6
0x000000007b800000 - 0x0000000080000000 size 0x04800000 type 0
0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
0x0000000100000000 - 0x000000087f000000 size 0x77f000000 type 6
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
CPU physical address size: 39 bits
MTRR: default type WB/UC MTRR counts: 6/8.
MTRR: WB selected as default type.
MTRR: 0 base 0x000000007b800000 mask 0x0000007fff800000 type 0
MTRR: 1 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
MTRR: 2 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
MTRR: 3 base 0x0000000090000000 mask 0x0000007ff0000000 type 0
MTRR: 4 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
CPU physical address size: 39 bits
BS: BS_WRITE_TABLES exit times (exec / console): 3 / 7 ms
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
CPU physical address size: 39 bits
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
FMAP: area COREBOOT found @ 350200 (4914688 bytes)
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
CBFS: Locating 'fallback/payload'
CPU physical address size: 39 bits
CBFS: Found @ offset 11a740 size 113de
Checking segment from ROM address 0xffc6a978
Payload being loaded at below 1MiB without region being marked as RAM usable.
Checking segment from ROM address 0xffc6a994
Loading segment from ROM address 0xffc6a978
code (compression=1)
New segment dstaddr 0x000df220 memsize 0x20de0 srcaddr 0xffc6a9b0 filesize
0x113a6
Loading Segment: addr: 0x000df220 memsz: 0x0000000000020de0 filesz:
0x00000000000113a6
using LZMA
Loading segment from ROM address 0xffc6a994
Entry Point 0x000fcfe9
BS: BS_PAYLOAD_LOAD run times (exec / console): 55 / 3 ms
Finalizing chipset.
HECI: No CSE device
Finalizing SMM.
APMC done.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 25 / 0 ms
mp_park_aps done after 0 msecs.
Jumping to boot code at 0x000fcfe9(0x7aac0000)
SeaBIOS (version rel-1.13.0-45-g6ada228)
BUILD: gcc: (coreboot toolchain vf2741aa632 2020-07-06) 8.3.0 binutils: (GNU
Binutils) 2.33.1
Found coreboot cbmem console @ 7abde000
Found mainboard Clevo N240BU
Relocating init from 0x000e0980 to 0x7aa3caa0 (size 54464)
Found CBFS header at 0xffb50238
multiboot: eax=7ab3ace0, ebx=7ab3aca4
Found 19 PCI devices (max PCI bus is 03)
Copying SMBIOS entry point from 0x7aa8a000 to 0x000f6100
Copying ACPI RSDP from 0x7aa9c000 to 0x000f60d0
table(50434146)=0x7aa9ec00 (via xsdt)
Using pmtimer, ioport 0x1808
table(324d5054)=0x7aa9fc70 (via xsdt)
Scan for VGA option rom
Running option rom at c000:0003
Turning on vga text mode console
SeaBIOS (version rel-1.13.0-45-g6ada228)
XHCI init on dev 00:14.0: regs @ 0x91300000, 18 ports, 64 slots, 32 byte
contexts
XHCI protocol USB 2.00, 12 ports (offset 1), def 3011
XHCI protocol USB 3.00, 6 ports (offset 13), def 3000
XHCI extcap 0xc0 @ 0x91308070
XHCI extcap 0x1 @ 0x9130846c
XHCI extcap 0xc6 @ 0x913084f4
XHCI extcap 0xc7 @ 0x91308500
XHCI extcap 0xc2 @ 0x91308600
XHCI extcap 0xa @ 0x91308700
XHCI extcap 0xc3 @ 0x91308740
XHCI extcap 0xc4 @ 0x91308800
XHCI extcap 0xc5 @ 0x91308900
/7aa3a000\ Start thread
XHCI init on dev 01:00.0: regs @ 0x91000000, 4 ports, 64 slots, 32 byte contexts
XHCI extcap 0x1 @ 0x91000800
XHCI protocol USB 3.01, 2 ports (offset 1), def 0
XHCI protocol USB 2.00, 2 ports (offset 3), def 19
XHCI extcap 0xa @ 0x91000850
/7aa39000\ Start thread
/7aa38000\ Start thread
AHCI controller at 00:17.0, iobase 0x91334000, irq 0
AHCI: cap 0xc324ff01, ports_impl 0x1
/7aa36000\ Start thread
|7aa36000| AHCI/0: probing
|7aa38000| Discarding ps2 data 41 (status=13)
Searching bootorder for: HALT
/7aa35000\ Start thread
Found 0 lpt ports
Found 0 serial ports
|7aa38000| keyboard self test failed (got ab not 0xaa)
\7aa38000/ End thread
|7aa35000| Searching bootorder for: /pci@i0cf8/pci-bridge@1d/*@0
\7aa35000/ End thread
|7aa36000| AHCI/0: link down
\7aa36000/ End thread
/7aa36000\ Start thread
/7aa35000\ Start thread
/7aa34000\ Start thread
/7aa33000\ Start thread
/7aa32000\ Start thread
/7aa31000\ Start thread
/7aa30000\ Start thread
/7aa2f000\ Start thread
/7aa2e000\ Start thread
/7aa2d000\ Start thread
/7aa2c000\ Start thread
/7aa2b000\ Start thread
/7aa2a000\ Start thread
/7aa29000\ Start thread
/7aa28000\ Start thread
/7aa27000\ Start thread
/7aa26000\ Start thread
/7aa25000\ Start thread
|7aa30000| XHCI port #7: 0x00200a03, powered, enabled, pls 0, speed 2 [Low]
/7aa24000\ Start thread
/7aa23000\ Start thread
/7aa22000\ Start thread
/7aa21000\ Start thread
|7aa30000| usb_hid_setup 0x7aa89220
|7aa30000| USB keyboard initialized
\7aa30000/ End thread
\7aa36000/ End thread
\7aa35000/ End thread
\7aa34000/ End thread
\7aa33000/ End thread
\7aa31000/ End thread
\7aa2f000/ End thread
\7aa2e000/ End thread
\7aa2d000/ End thread
\7aa2c000/ End thread
\7aa2b000/ End thread
\7aa2a000/ End thread
\7aa29000/ End thread
\7aa28000/ End thread
\7aa27000/ End thread
\7aa26000/ End thread
\7aa25000/ End thread
|7aa32000| XHCI port #5: 0x00200603, powered, enabled, pls 0, speed 1 [Full]
|7aa32000| xhci_realloc_pipe: reconf ctl endpoint pkt size: 8 -> 64
\7aa32000/ End thread
\7aa3a000/ End thread
\7aa24000/ End thread
\7aa23000/ End thread
\7aa22000/ End thread
\7aa21000/ End thread
|7aa39000| XHCI no devices found
\7aa39000/ End thread
All threads complete.
Scan for option roms
Press ESC for boot menu.
Searching bootorder for: HALT
drive 0x000f6070: PCHS=0/0/0 translation=lba LCHS=1024/255/63 s=1000215216
Space available for UMB: d0000-ec800, f5920-f6070
Returned 16384 bytes of ZoneHigh
e820 map has 12 items:
0: 0000000000000000 - 000000000009fc00 = 1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 000000007aa4e000 = 1 RAM
4: 000000007aa4e000 - 0000000080000000 = 2 RESERVED
5: 00000000e0000000 - 00000000f0000000 = 2 RESERVED
6: 00000000fe000000 - 00000000fe010000 = 2 RESERVED
7: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
8: 00000000fed40000 - 00000000fed45000 = 2 RESERVED
9: 00000000fed80000 - 00000000fed85000 = 2 RESERVED
10: 00000000fed90000 - 00000000fed92000 = 2 RESERVED
11: 0000000100000000 - 000000087f000000 = 1 RAM
enter handle_19:
NULL
Booting from Hard Disk...
Booting from 0000:7c00
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